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Digital IC Design Engineer

  • 全職

Digital Design Engineer works on high-performance analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The successful candidate in this role will assist with engineers in analog/mixed-signal team to develop and verify the digital engine for high-performance data converter. And, you will be responsible for synthesis and place-and-route flow for digital engine in for high-performance data converter.

工作條件

  • 接受身份: 上班族、應屆畢業生、外籍人士、學生實習
  • 工作經歷: 不拘
  • 學歷要求: 學歷不拘
  • 語文條件: 英文 -- 聽 /精通、說 /中等、讀 /精通、寫 /精通
    中文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 工作技能: 數位電路驗證、數位電路分析設計、數位晶片產品開發
  • 其它條件: * BS with 2+ year of experience in high-performance digital or mixed-signal IC development in deep submicron CMOS processes
    * Understanding of digital design for mixed-signal control loops and writing Verilog code to control and calibrate analog circuits
    * Knowledge of Verilog RTL code including state machines, adders, multipliers, combinatorial logic and complex mathematical operators such as differentiator and integrator
    * Familiar with behavioral Verilog codes including System-Verilog, Verilog-AMS, VHDL-AMS, Wreal, VHDL
    * Ability to write full testbenches for verifications in digital and AMS
    * Familiar with design synthesis tool, and place and route tool
    * Familiar with Cadence Encounter tool
    * Familiar with timing closure and static timing analysis tools
    * Extensive experience with synthesis, and place and route flows in deep submicron CMOS process such as 28nm HPC, 16nm FF+/FFC
    * Experience with scan chain vector generation and verification
    * Deep understanding in high speed multi-clock gating design
    * Must be able to work independently according to schedules and be team player
    * Strong written and verbal communication skills

福利制度

◆ 分紅 / 配股
 1.員工認股
◆ 制度類
 1.績效獎金
◆ 請 / 休假制度
 1.週休二日
 2.不扣薪病假
 3.不扣薪事假

更新日期:2019-07-21

應徵方式

  • 職務聯絡人: 駱智峯
  • 聯絡E-Mail: 我要應徵
  • 洽:
  • 洽: 不接受親洽
  • 它: Preferably email (lok@caelustech.com) or by phone +852 66457979.

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年50%
5~10年0%
10年以上50%
學歷分佈
碩士及以上0%
大學100%
專科0%
高中0%
高中以下0%
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