全部的工作機會

1. Review WIP/Backlog to release Assembly build instruction to OSAT. 2. Monitor OSAT WIP movement to ensure on time delivery 3. New orders/backlog ship dates commit 4. Manage backlog pull-in/push out request from customers 5. Timely OSAT inventory/WIP transaction in AX to ensure inventory accuracy 6. Annual physical inventory count in OSATs 7. Drive OSAT to improve cy

1. Manage wafer foundry and solve all engineering related issues occurred in wafer foundry 2. Monitor foundry process control and yield performance, yield improvement 3. Manage new product tapeout, mask tooling, engineering preparation, schedule control, corner splits, DOE before mass production 4. Coordinate with wafer foundry for technical Q&A with internal R&D team 5. Foundry technology

1. Design RTL/Logic using Verilog 2. Simulate and develop IPs and Subsystems 3. Validate silicon and debug

1. Analog circuit design and verification, such as OPAMP, Bandgap, ADC/DAC, PLL, and etc. 2. Power management circuit design and verification, such as LDOs, Charge Pumps, Switching Regulators, Gamma reference, and etc. 3. Whole chip integration with mixed-signal circuit. 4. HV I/O and ESD design.

1. Support Chip Design Engineer on Signal Integrity testing and Debugging 2. Support Customers PCIE projects from design-in to mass-production. 3. Team work with RD, FAE and QA on problems solves.

1. Lead a team of a major subsystem of a large SOC 2. Architect of SOC subsystem including microarchitecture documentation 3. Demonstrate an expert knowledge of System Verilog (SV) or similar verification language 4. Demonstrate an expert knowledge of Verilog for chip design and verification 5. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, tim

IC ATE test development ： test spec create, PCB schematics development and layout review, ATE program development/ debug/fine tune, STD/STDF production data analyses. *Work frequently at subcons in Hsinchu *Office in Taipei

1. 5+ years experiences with MS in EE 2. Hands on experiences on the design and validation of wireline high speed silicon 3. Experiences with strong design capability for the 10Gbps+ wireline data transfer 4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus

IC ATE test development ： test spec create, PCB schematics development and layout review, ATE program development/ debug/fine tune, STD/STDF production data analyses. *Work frequently at subcons in Hsinchu *Office in Taipei

1. Demonstrate an expert knowledge of System Verilog (SV) or similar verification language 2. Demonstrate an expert knowledge of Verilog for chip design and verification 3. Must be able to read specifications, create a MAS, then implement the design 4. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and

1. Lead a group of Production Control for production demand analysis and OSAT supply management. Coordinate internal demands, drive OSAT capacity support, set priority to optimize and balance Parade demand vs. OSAT supply. 2. Production material, e.g. substrates, lead frame, memory (DRAM, SPIROM), management (demand and schedule) 3. NPI (New Production Introduction) bring-up and ensure flawless tr

1. Responsible for display and image processing algorithm development. 2. Participate in system architecture definition, algorithm developing and evaluation, algorithm implementation and simulation.

1. 10+ years experience with MS in EE or CS 2. Hands on silicon design and bring up experiences 3. Experiences with data communication protocols such as PCI Express, SuperSpeed USB, SATA, etc. 4. Experiences in mixed signal design with good understanding of analog circuit design 5. Design experience with PCIe 3.0 and 4.0 is a plus

1. Responsible for display and image processing algorithm development. 2. Participate in system architecture definition, algorithm developing and evaluation, algorithm implementation and simulation.