Staff Design Engineer (Analog IC, Hsinchu)

• Strong track record designing successful high volume power management ICs • Skilled at transistor level design of all types of sub-blocks • Experience and knowledge of DC-DC controllers and common architectures • Deep understanding of semiconductor manufacturing, layout and devices • Use of Cadence software and tools for analog IC design • Master analog behavioral modeling using Verilog-A and AMS simulation flow • At least 10 years working in analog IC Design for power management ICs • Masters or equivalent in Electrical engineering