(Sr.) Digital Vertification Engineer (Hsinchu 新竹)

Qualifications: • BSEE +5 years or MSEE +3 years of relevant experience. At least 3 years of digital verification, including test writing and verification of several products • Experience with using the Cadence Virtuoso software and AMS simulation environment • Comfortable with exploring the analog schematic hierarchy in Cadence • Able to write and debug System Verilog models. Previous real number modelling experience a plus • Can create thorough block and system level SV assertions • Experience in debugging simulation issues and bug identification • A good understanding of UVM, and the ability to import an environment from an existing project and improve upon it • Strong scripting skills is a highly desirable (csh, Python and TCL) • Able to work well in a remote team environment, including good communication and inter-personal skills • Self-starter able to manage his/her own time effectively