多方科技股份有限公司

[Responsibilities] ★ Define and maintain the end-to-end low power design flow and methodology for SoC projects ★ Specify and implement power intent using UPF or CPF, supporting multi-voltage and power domain strategies ★ Collaborate with RTL teams to ensure low power design practices are followed, including domain partitioning, retention strategies, and isolation techniques ★ Work with physical design teams to integrate low power features during synthesis, floorplanning, and place-and-route stages ★ Drive power-aware verification, including simulation and static checks ★ Develop and maintain automation scripts to support consistent and scalable low power flows ★ Assist in RTL-level power estimation and guide design teams to optimize power early in the design cycle ★ Correlate pre-silicon estimates with post-silicon measurements for flow validation and tuning ★ Serve as a cross-functional liaison between architecture, RTL, PD, and verification teams to ensure power intent consistency and alignment ★ Occasional business travel across APAC and other regions may be required [Minimum Qualifications] ★ Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of relevant experience ★ Proven hands-on experience with low power design techniques, such as DVFS, clock gating, power gating, and state retention ★ Proficiency in power intent specification using UPF or CPF ★ Strong understanding of RTL-to-GDSII flow, especially in handling low power features ★ Experience with power-aware simulation, static checks, and signoff tools ★ Scripting experience with Python, Tcl, or Shell [Preferred Qualifications] ★ Experience setting up CLP flows from scratch or leading low power methodology development ★ Familiarity with SoC-level power domain partitioning and hierarchical power control ★ Comfortable working in a globally distributed, cross-disciplinary engineering team ★ Experience with EDA tools such as VCS/Verdi, Xcelium, PowerArtist, SpyGlass, Fusion Compiler, or Innovus ★ Experience with RTL-level power modeling and estimation ★ Exposure to post-silicon power validation and correlation

[Responsibilities] ★ Analyze and optimize SoC power and performance trade-offs at block and system level ★ Define and implement power management strategies across various IPs and subsystems ★ Work with architecture and design teams to evaluate new feature impact on power and performance ★ Develop use-case-driven workloads for pre-silicon power/performance analysis ★ Collaborate with verification and software teams for modeling and validation ★ Correlate pre-silicon analysis with post-silicon measurements to enhance model accuracy ★ Occasional business travel across APAC and other regions may be required [Minimum Qualifications] ★ Master's degree in Electrical Engineering or a related field with 5+ years of relevant experience, or a PhD in a related field. ★ 3–5 years of hands-on experience in SoC power/performance architecture or relevant chip design roles ★ Solid experience in low-power design techniques, such as DVFS, clock gating, and power retention ★ Familiarity with power analysis tools (e.g., PrimePower, PowerArtist, PT-PX) [Preferred Qualifications] ★ Strong understanding of SoC microarchitecture, including CPU, interconnect, and memory hierarchy ★ Proficient in scripting languages such as Python, Perl, Tcl, or Shell for automation and data processing ★ Comfortable working in a globally distributed, cross-disciplinary engineering team ★ Excellent problem-solving skills, with the ability to work independently and collaborate across teams ★ Experience with performance modeling or benchmarking is a plus ★ Exposure to post-silicon power/performance bring-up and correlation is a strong advantage

[Responsibilities] ★ Own and execute RTL synthesis flow from front-end handoff to netlist delivery ★ Develop and maintain timing constraints (SDC) and power intent (UPF) for synthesis and signoff ★ Analyze and optimize QOR (Quality of Results) for timing, area, and power ★ Support logic equivalence checking (LEC) and ECO implementation ★ Collaborate with RTL, STA, and PD teams to ensure timing closure and flow consistency ★ Drive methodology improvements and automation for synthesis and constraint management ★ Assist in low power feature integration and support multi-voltage domain synthesis ★ Provide guidance on RTL coding styles and constraint best practices ★ Correlate synthesis results with physical implementation feedback ★ Occasional business travel across APAC and other regions may be required [Minimum Qualifications] ★ Master’s degree in Electrical Engineering, Computer Engineering, or related field ★ 5+ years of hands-on experience in RTL synthesis and timing closure ★ Proficiency in EDA tools such as Synopsys Fusion Compiler, Synopsys Design Compiler, Formality, PrimeTime ★ Solid understanding of RTL-to-GDSII flow and synthesis optimization techniques ★ Experience with constraint development (SDC) and low power design using UPF ★ Strong scripting skills in Python, Tcl, or Shell ★ Excellent problem-solving and cross-functional communication skills [Preferred Qualifications] ★ Experience with advanced synthesis methodologies and flow development ★ Familiarity with hierarchical SoC designs and large-scale integration ★ Knowledge of low power techniques including power gating, retention, and isolation ★ Exposure to ECO flows and logic equivalence verification ★ Experience with EDA tools such as Fusion Compiler, SpyGlass, Innovus, or PowerArtist ★ Comfortable working in a globally distributed engineering environment ★ Experience correlating pre-silicon synthesis results with post-silicon measurements

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow

[Responsibilities] ★ Experienced in Video Codec (H.264/ H.265) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow