千逢科技股份有限公司

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware Design • Generative AI NPU design and hardware architecture • Memory system design (cache controller, DRAM controller) • Interconnect/Fabric design • Low power technology expertise • High-speed interface design (HW/SW collaboration) • High-performance virtualization designs Programming Languages: Strong programming skills in languages like Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

Job Title: Generative AI Models Optimization Engineer - NPU Hardware Job Description: Overview: We are seeking a skilled and innovative Generative AI Models Optimization Engineer to join our dynamic team. In this role, you will be responsible for developing and optimizing generative AI models specifically tailored for Neural Processing Unit (NPU) hardware. As a key member of our AI research and development team, you will play a crucial role in advancing the efficiency and performance of our cutting-edge AI applications. Responsibilities: Generative AI Model Development: Design, implement, and optimize generative AI models for deployment on NPU hardware. Collaborate with cross-functional teams to understand application requirements and tailor models for specific use cases. NPU Hardware Optimization: Analyze and profile NPU hardware architecture to identify optimization opportunities. Implement and fine-tune algorithms to maximize performance and minimize resource utilization on NPUs. Performance Evaluation: Conduct rigorous testing and performance evaluations to ensure generative AI models meet quality standards and deliver optimal results on NPU hardware. Collaborate with QA teams to establish benchmarking criteria and validate model performance across various scenarios. Algorithmic Efficiency: Work on enhancing algorithmic efficiency to ensure that generative AI models are capable of real-time generation while maintaining high-quality outputs. Implement and experiment with state-of-the-art techniques for model compression and quantization. Collaboration: Collaborate with hardware engineers, software developers, and researchers to integrate optimized models into end-to-end AI systems. Provide technical expertise and guidance to cross-functional teams. Documentation: Document optimization methodologies, best practices, and performance results. Create clear and comprehensive documentation for both technical and non-technical stakeholders. Qualifications: Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. Proven experience in developing and optimizing generative AI models. Solid understanding of Neural Processing Unit (NPU) architecture and hardware constraints. Proficiency in programming languages such as Python, TensorFlow, PyTorch, or C++. Experience with model compression, quantization, and other optimization techniques. Strong problem-solving skills and the ability to work in a collaborative team environment. Preferred Skills: Familiarity with deep learning frameworks and libraries. Knowledge of hardware acceleration technologies and frameworks. Experience with parallel computing and distributed systems. Previous work on AI applications in computer vision, natural language processing, or speech recognition is a plus. If you are passionate about pushing the boundaries of AI optimization on NPU hardware and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of generative AI applications.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware design verification : • Develop verification environment. • Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building, maintaining testbenches and their components using UVM-based methods. • Functional coverage and code coverage. • Generating the random testcases for NPU design,and providing debug reports. • Develop the auto-verifying environment using scripting languages like Perl and Python. Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

Job Title: AI Compiler Engineer Job Description: Overview: We are seeking a skilled and motivated AI Compiler Engineer to lead the development of our AI compiler for the Neural Processing Unit (NPU). As part of our team, you will play a critical role in transforming high-level neural network workloads (such as CNNs and transformer models) into efficient machine code that maximizes inference performance, minimizes power consumption, and optimizes memory usage. Responsibilities: 1. Compiler Development: • Design and develop an AI compiler that translates high-level neural network descriptions (in frameworks like TensorFlow, PyTorch, or ONNX) into optimized machine code for the NPU. • Implement parsing algorithms to analyze neural network graphs and extract relevant information for compilation. 2. Optimization Strategies: • Optimize the computational graph by applying techniques such as operator fusion, kernel selection, and memory layout transformations. • Minimize inference time, reduce power consumption, and optimize memory footprint through intelligent code generation. 3. Performance Profiling and Analysis: • Profile compiled code to identify bottlenecks and areas for improvement. • Collaborate with hardware architects to understand NPU microarchitecture and tailor optimizations accordingly. 4. Code Generation and Lowering: • Generate efficient machine code from the intermediate representation of neural network operations. • Ensure compatibility with the NPU's instruction set architecture. 5. Integration and Testing: • Integrate the AI compiler into the overall software stack, including runtime libraries and drivers. • Develop test suites to validate correctness, performance, and compatibility across various neural network models. 6. Documentation and Communication: • Document design decisions, algorithms, and implementation details. • Collaborate with cross-functional teams, including hardware engineers, software developers, and researchers. Qualifications: • Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. • Minimum of 3 years of experience in compiler development, preferably with exposure to AI or machine learning. • Proficiency in C/C++/Python programming and familiarity with compiler construction. • Knowledge of neural network frameworks (TensorFlow, PyTorch, etc.) and their intermediate representations. • Experience with performance profiling tools and optimization techniques. • Understanding of machine learning concepts and hardware architectures. • Familiarity with data structures, optimization algorithms, and DevOps tools (such as Git, CI/CD pipelines). • Strong problem-solving abilities and attention to detail. • Excellent communication skills for collaborating with cross-functional teams. Preferred Skills: • Familiarity with deep learning frameworks and libraries. • Knowledge of hardware acceleration technologies and frameworks. • Experience of tensor computation and optimization. • Previous work in compiler for CPU, GPU, DSP, NPU is a plus. If you are passionate about compiler engineering, AI optimization, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI acceleration.

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) The Product Marketing & Strategy Manager for AI NPUs will be responsible for defining and executing go-to-market strategies, driving product positioning, and identifying key market opportunities. This role requires a deep understanding of AI workloads, semiconductor trends, and customer needs to develop and promote cutting-edge NPU solutions for edge and cloud AI applications. Key Responsibilities: 1. Product Strategy & Roadmap Development •Define product positioning, value proposition, and differentiation strategies for AI NPUs. •Collaborate with R&D and engineering teams to define product specifications based on market demands. •Develop a long-term roadmap for AI NPU solutions, ensuring alignment with industry trends and customer needs. 2. Market Research & Competitive Analysis •Conduct market research to identify trends in AI accelerators, semiconductor technology, and application verticals (e.g., healthcare, automotive, IoT, data centers). •Analyze competitive landscape, including key players like NVIDIA, AMD, Intel, and emerging AI chip startups. •Provide insights on pricing models, industry benchmarks, and customer pain points. 3. Business Development & Go-To-Market Strategy •Define GTM (go-to-market) strategies, including channel partnerships, ecosystem collaborations, and customer engagement plans. •Work closely with sales teams to create compelling sales strategies and value propositions. •Establish key partnerships with software developers, AI model providers, and cloud service providers. 4. Technical & Customer Engagement •Serve as the technical bridge between product, sales, and customers, explaining AI NPU capabilities and performance benefits. •Gather customer feedback to refine product features and enhance user adoption. •Conduct training and workshops for sales teams, partners, and customers on AI NPU architecture and applications. 5. Thought Leadership & Industry Influence •Represent the company at AI and semiconductor conferences, trade shows, and industry events. •Develop whitepapers, blogs, and marketing content that showcase the value of AI NPU solutions. •Build relationships with key stakeholders, including AI researchers, industry analysts, and technology influencers.