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台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
意見回饋
廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

Design Verification Engineer

  • 全職

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
2.Create verification environments using SystemVerilog, SystemC or UVM.
3.Identify and write all types of coverage measures for stimulus and corner-cases.
4.Debug tests with design engineers to deliver functionally correct design blocks.
5. Close coverage measures to identify verification holes and to show progress towards tape-out.

工作條件

  • 接受身份: 上班族、外籍人士
  • 工作經歷: 二年以上
  • 學歷要求: 大學以上
  • 語文條件: 不拘
  • 其它條件: 1.Bachelor's degree in Electrical Engineering or Computer Science.
    2.Experience in verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog or SystemC for ASICs and/or SoCs.
    3. Experience with the creation of and usage of verification components and environments in a standard verification methodology such as UVM, OVM, or VMM.

    Preferred qualifications:
    1.Master's degree in Electrical Engineering or Computer Science.
    2.2+ years experience in verification of SoC
    3. Experience in one or more of the following application domains, is a plus
    - Defining coverage space and writing coverage model
    -Verification IP (VIP) development or usage
    - AMBA bus protocols
    - Verification using SystemC
    -Neural network

    Location: Hsinchu

福利制度

◆ 分紅/配股
1.員工認股
◆ 獎金/禮品類
1.年終獎金
◆ 休閒類
1.部門聚餐
2.運動日
◆ 制度類
1.員工制服
2.伙食費
3.績效獎金
◆ 請/休假制度
1.週休二日
2.特休/年假(優於勞基法之特休天數,到職即享10天特休)
3.不扣薪病假七天
◆ 其他
1.健康檢查

更新日期:2021-10-19

應徵方式

  • 職務聯絡人: Tiny
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年100%
3~5年0%
5~10年0%
10年以上0%
學歷分佈
碩士及以上100%
大學0%
專科0%
高中0%
高中以下0%
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