求職服務專線
台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
意見回饋
廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

Physical Design Engineer, Senior to Staff (3017925)

  • 全職

QCTs CPU Subsystem Team in Taiwan is actively seeking engineers for the CPU Subsystem Physical Design Team. As a physical design engineer you will innovate, develop, and implement CPU cores using state-of-the-art tools and technologies. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design implementations for high performance SoCs in sub-7nm process for mobile space. You will be responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power CPU’s designs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification.

The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design CPU solutions from netlist and timing constraints to the final product.

工作條件

  • 工作經歷: 五年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件: Minimum qualifications

    · Bachelor’s degree in Electrical Engineering
    · 5+ years of experience in Physical Design Implementations for deep Sub-micron designs.
    · Place and Route Tool experience on Cadence Innovus and/or Synopsys ICC2
    · Timing Closure experience in Synopsys PTSI
    · Formal Verification Experience
    · ASIC Physical Verification experience
    · ASIC PDN techniques and implications on CPU implementations

    Preferred qualifications

    · MS degree in Electrical Engineering; 10+ years of practical experience
    · Experience in timing flows with industry standard tools.
    · Experience in all aspects of timing closure for multi-clock domain designs.
    · Experience in deep submicron process technology nodes is strongly preferred.
    · Experience with STA on large SOC with multi-scenario timing closure.
    · Experience with Timing ECO techniques and implementation.
    · Knowledge of library cells and optimizations.
    · Familiar with circuit modeling, transistor fundamentals and worst case corner selection.
    · Solid understanding industry standard tools for synthesis, place & route and tapeout flows.
    · Good communication skills to work with different teams to accurately describe issues and follow them through for completion.
    · Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies.
    · Knowledge of all aspects of timing including noise, cross-talk and others.
    · Knowledge of basic SoC architecture and HDL languages like Verilog.
    · 2+ years of work experience in a role requiring interaction with Senior Leadership (eg. Director level and above)

福利制度

Along with quality, life-enhancing programs. When we say the benefits of working at Qualcomm are many, you’ll see we mean that quite literally. Just take a look…

The benefits listed below apply to the employees of Qualcomm Taiwan Corporation & Qualcomm Communication Technologies Limited located in Taiwan

National Health and Labor Insurance
National Retirement Scheme
Public Holidays
Paid Maternity Leave
Paid Paternity Leave
Annual Leave
Education Assistance

更新日期:2022-01-13

應徵方式

  • 職務聯絡人: HR
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: Please apply via www.qualcomm.com/careers and refer to req number 3017925

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年0%
5~10年0%
10年以上100%
學歷分佈
碩士及以上67%
大學33%
專科0%
高中0%
高中以下0%
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