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FPGA Engineer (Server )

  • 全職

Position Description:
Lenovo is a US $46 billion global Fortune 500 company and a leader in providing innovative consumer, commercial and enterprise technologies. Its has successfully embarked into intelligent transformation” to capitalise on the rapid growth of the internet of things (IoT) market globally, as well as the wider adoption of artificial intelligence (AI) and automation. Globally, our product lines include a full range of commercial and consumer PCs, servers and workstations, and a family of mobile internet devices including tablets and smart phones. We design and build our products to bring progress to the world. Serving customers in more than 160 countries, we take our inspiration from the drive and imagination of the people who make things happen; our technology helps those who do, do better.


At Lenovo we employ more than 60,000 people worldwide and our people share a common aspiration to be the very best. Whether serving our customers, working as a team or contributing to the community, we are working to build a unique company. A company that delivers unparalleled products created and supported by people with a wealth of different cultures and experiences. Our strength lies in this diversity. We are dedicated to fostering an environment that encourages entrepreneurism and ownership. A workplace where people's talents can be challenged and their efforts recognised and rewarded. We employ fantastic people…come join the fun!

About Role:

As part of the HPC server team, this FPGA engineer is expected to work with peer functions as a team to develop the leading edge Lenovo high performance computer offerings.

Responsibilities

-Responsible for server system FPGA/CPLD development, verification, and maintenance
-Maintain relevant design document.
-Work closely with worldwide hardware and firmware team for issue analysis.
Position Requirements: Basic Qualifications
- MS degree in Electrical Engineering, Computer Engineering or equivalent practical experience.
- 5+ years of experience doing digital design, simulation, hardware bringup and debug.

Desired skills
- Familiarity with VHDL/Verilog coding and FPGA/CPLD design flow is a must
- Familiarity with Altera/Xilinx EDA design tool.
- Familiarity with FPGA/CPLD design in server application and multiple bus protocols including I2C / power sequence / SPI / LPC / SGPIO / I2C switch/ UART / PWM / eSPI
- Strong HW and x86 architecture knowledge is a plus.
- Fluent English written and verbal communication skills.
- Integration and test experience
- Highly self-motivated, able to work independently in a lab environment.

工作條件

  • 工作經歷: 不拘
  • 學歷要求: 專科 大學 碩士
  • 語文條件: 不拘
  • 其它條件: 未填寫

福利制度

法定項目

其他福利

1. Employee health exam program
2. Paid sick leave
3. Group insurance
4. Employee Welfare Committee activities
5. Flexible Working Hours & Work From Home Options

Leave / 假期
1. Annual leave top up with selected special holiday up to 7 days
2. 84 個日曆天假期(其中 60 天為產假,24 天為產後恢復假) / "Maternity Leave" 84 calendar days of leaves (including 60 days of Maternity Leave and 24 days of Recovery Leave)
3. 產檢假七日 / Seven(7) days of Prenatal exam leave
4. 全薪病假 / Fully Paid Sick Leave
5.親職假20日 / 20 days Paternity leave

更新日期:2022-01-13

應徵方式

  • 職務聯絡人: Chiam Jia Xin
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年0%
5~10年50%
10年以上50%
學歷分佈
碩士及以上100%
大學0%
專科0%
高中0%
高中以下0%
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