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RTL Design Engineer - RISC-V CPU

  • 全職

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP & SoC IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our shown success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

SiFive was founded and is actively run by the developers of RISC-V. If you are passionate about working with industry leaders and innovators, then send us your application today!


As a CPU Microarchitect/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.

Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.

Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.

Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.

工作條件

  • 接受身份: 上班族、外籍人士
  • 工作經歷: 四年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /中等、寫 /中等
  • 其它條件: Requirements:

    4+ yrs of recent industry experience in CPU design.

    Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.

    Knowledge of RISC-V architecture is a plus.

    Experience with Scala and/or Chisel is a plus.

    Attention to detail and a focus on high-quality design.

    Ability to work well with others and a belief that engineering is a team sport.

    Knowledge of at least one object-oriented and/or functional programming language.

    BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

福利制度

法定項目

其他福利

SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health benefits, employee stock option program, and much more.

In addition to these, we provide regional benefits including team-building events, annual physical examination, and education reimbursement for the employees in Taiwan.

We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you.

更新日期:2021-09-22

應徵方式

  • 職務聯絡人: Grace Chen
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

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