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IC設計類: AI Design Center - ASIC Digital Design Engineer (有經驗或應屆畢業生皆歡迎) (新竹)

  • 全職

Job Description:
The selected candidate will be a key member of the Synopsys DesignWare Processor team in Hsinchu and involved in the development of leading edge DesignWare processor IP products such as NN accelerators, vision processors, as well as high-performance or energy-efficient general purpose processors.
The responsibility could vary from architecture analysis, micro-architecture, logic design and implementation, formal verification, simulation verification, as well as related engineering flows and environments, depending on individual’s capability and career development, which would include but not limited to related creation, implementation, analysis, debugging, and optimization work. In addition, the candidate would have a great opportunity to collaborate cross-team and cross-site in algorithm analysis, methodology development, quality improvement, product delivery, as well as SoC implementation and system bring-up, or any other engineering works that could be needed for the overall ARC team business.

ASIC Design Engineer Introduction: https://www.youtube.com/watch?v=co3BC-BUTLg

Job Requirements:

Master degree in EE or CS related engineering major is required as a minimum from a reputed college
• Up to 4 years of experience in digital design or verification
• Microprocessor architecture knowledge
• HDL and Verification languages: SystemVerilog, Verilog
• Micro-architecture and RTL design, or verification methodologies such as UVM/OVM, functional formal, functional coverage
• Programming skills: SystemVerilog, C/C++, plus Python, shell scripts, or assembly
• Tools for RTL linting, simulation, and synthesis are recommended
• Tools for functional formal, functional coverage, teamwork collaboration (continuous integration, source control management, issue tracking, etc.), or ADL-based generation (such as Synopsys ASIP Designer) are plus
• Experience with multi-site development is helpful
• Written and verbal communication skills:
• Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports
• Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation for leadership review
• Ability to follow disciplines describing issues and changes in track systems
• Analytical skills:
• Analysis of signoff requirements for product releases
• Ability to analyze QoR and verification results for major milestone reviews and assessments.
• Self-motivated team player able to thrive in a fast-paced engineering environment

工作條件

  • 接受身份: 上班族
  • 工作經歷: 三年以上
  • 學歷要求: 大學以上
  • 語文條件: 不拘
  • 其它條件: 未填寫

福利制度

法定項目

其他福利

除法定福利以外,所有正式員工可享有以下公司贊助之福利:

1. 保險福利 - 公司全額負擔勞保、健保、團保

2. 福利活動 – 福委會社團活動、旅遊補助、生日/ 三節禮金、婚喪喜慶及生育補助、定期健康檢查

3. 教育訓練制度 – 鼓勵不斷的學習及自我成長,創造活潑的學習環境,配合個人的長短期生涯規劃,提供完善的教育訓練制度,包括內訓及外訓,技術性及非技術性訓練

4. 員工購股(ESPP)

5. 優於勞基法之特休假及部分全薪之事病假

6. 另享每月各項現金津貼

更新日期:2021-10-12

應徵方式

  • 職務聯絡人: HR
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內6-10人應徵
經歷分佈
新鮮人33%
1~3年33%
3~5年0%
5~10年0%
10年以上33%
學歷分佈
碩士及以上67%
大學17%
專科0%
高中0%
高中以下0%
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