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台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
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Principal Engineer - DFT (Wireless SOC)

  • 全職

Job Description:
In this position, you will be responsible for all the DFT related matters in Microchip's Wireless SoC Development. Your scope of work includes but not limited to:
• Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools
for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan.
• Work closely with front-end team to ensure the logic structures permit and are suitable for DFT insertion.
• Work closely with front-end and back end implementation team to ensure that DFT implementation does not impact the functionality and timing of the chip
• Develop timing constraint (SDC) files for DFT modes and corners
• Perform STA and drive for timing closure in DFT modes and corners
• Develop DFT test benches
• Perform RTL/Gate-level simulation to ensure the post-layout design passed the DFT test benches
• Prepare and Debug DFT test patterns for production team
• Develop DFT methodology to improve runtime and design testability
• Perform DFT sign-off checklist and reviews

Key Responsibilities:
• Candidate will provide hands on technical leadership to the WSG Silicon Development Team in the area of DFT implementation.
• Drive DFT Integration Plan, Implementation and Verification (SCAN/ATPG/MBIST/BSCAN)
• Participate in Synthesis, Power Optimization, Signal Integrity, and Static Timing methodologies for Microchip’s wireless SoC development.
• Participate in SoC timing budgeting, constraint analysis, optimization, and sign-off timing closure.
• Participate in front-end low power implementation and optimization using UPF
• Participate in Formal Verification (logic equivalency)
• Participate in SoC development planning and scheduling.
• Participate in Library and Memory IP selection (benchmarking/evaluations), characterization, and configuration.
• Participate in SoC development planning and scheduling.
• Continuously improve DFT flows and methodologies.
• Assist in the validation and debug silicon products in support of release to production.
• Interface with applications, product and test engineering, marketing, development systems, technology development, CAD, layout and other design organizations

工作條件

  • 接受身份: 上班族
  • 工作經歷: 八年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件: Required Skills:
    • Expertise in Design for Test, ATPG, MBIST, and JTAG preferably with Mentor Graphics /Tessent tools.
    • Familiarity with Synthesis, Formal Verification, and Static Timing Analysis preferably with Synopsys tools.
    • Familiarity with Verilog, Verilog simulation, and debug.
    • Familiarity with Tcl, Perl, Python, and Shell scripting.
    • Familiarity with low-power implementation techniques (UPF).
    • Familiarity with early-stage DFT Design Rule checking to reduce design iterations.
    •Strong understanding of digital implementation tools and flow
    •Familiarity with MIPS or ARM cores.
    • Experience with advance technology nodes (65nm and below).
    • Good communication and teamwork skills.
    • English Language proficiency highly desirable.

    Desired Skills:
    • Experience with Frontend or Backend Implementation flow
    • Experience with ARM/MIPS processor-based subsystem
    • Knowledge of Programming Languages such C/C++
    • Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired
    • Experience working on Mixed Signal SOC, WiFi, WLAN, or Bluetooth products

    Other:
    • We are looking for candidates who are self-motivators, energetic, and team players. Candidates will need to do some light travel to support the global wireless team.

福利制度

-年度特休假優於勞基法
-全額補助團保(員工本人、配偶及子女)
-年度健康檢查補助
-婚喪喜慶及生育補助、三節禮金、生日禮金
-著重國際人才培訓,提供教育訓練方案,外訓課程補助
-Wellness Program

更新日期:2021-07-28

應徵方式

  • 職務聯絡人: 陳小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: Any interested parties, please provide English resume.

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