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台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
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廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

數位ic驗證工程師/主管 (DV)--新竹

  • 全職

Job description
• Work with IC architects and designers to decide the specifications and verification plans
• Ensure functional and code coverage of complex RTL design blocks
• Work with software team to enable software development and testing

Job requirement
• BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design and verification.
• 5+ years of industry experience is preferred.
• Experience in SoC or ASIC verification for at least several chip tapeout-out and volume production projects
• Familiarity with UVM, can setup a UVM test environment and create UVM models from scratch is required.
• Experience in design, simulation and debug EDA tools.
• Experience in RTL. Verilog and SystemVerilog are required.
• Familiarity with script programming such as shell script, make, Python, etc.
• Skills in system verification such as FPGA prototype buildup and debug are desirable.
• familiar with CAD flow, can help to setup company design flow environment such as LEC/Linting/CDC/synthesis flow are preferred.
• Willing to take on challenges, and effective English communications and co-work with other team members.

Compensation and benefits
 Salary + bonus: NTD 1M-4M/year depends on capability
 Stock option offerings
 Generous PTO and benefits
 High growth potential

工作條件

  • 工作經歷: 四年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /精通、寫 /精通
  • 工作技能: 撰寫硬體語言程式、基礎數位電路、數位晶片產品開發、數位電路分析設計、數位電路驗證
  • 其它條件: Verilog, System Verilog, UVM,

福利制度

• Competitive salary 1~>3M
• Stock option offerings
• Generous PTO and benefits
• High growth potential
美式管理 彈性上下班時間

更新日期:2021-11-22

應徵方式

  • 職務聯絡人: Chester/Kate
  • 聯絡E-Mail: 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年50%
3~5年50%
5~10年0%
10年以上0%
學歷分佈
碩士及以上50%
大學50%
專科0%
高中0%
高中以下0%
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