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台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
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廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

資深類比/混成信號積體電路設計工程師/主管(Senior Analog/Mixed-signal Design Engineer/Manager)

  • 全職

As an analog/mixed-signal ASIC Design Engineer, the individual’s primary responsibility will be
analog or mixed-signal integrated circuit (IC) design.
This will include block/function definition, specification, design, simulation and verification of
blocks on Mixed Signal ASICs

Key Qualifications
• BSEE or MSEE with 5+ years of experience in analog or mixed-signal ASIC design.
• Proficient knowledge on design and verification on at least one or
more of the following: PLL, ADC/DAC, LDO or switching regulator.
• Proven track record of realizing design into shipped silicon.
• Proficient with simulation tools such as spectre, hspice, afs and MATLAB.
• In depth knowledge of semiconductor device parameters and modeling of modern CMOS technology
• Capable of mask design planning and work with layout engineers.
• Knowledge of back-end flow such as LVS, DRC, and parasitic extraction.
• Experience in hands-on post-silicon evaluation and debugging activities.
• Experience in image or other sensor IC a plus.
• Experience in high voltage design a plus.
• Knowledge of DSP blocks such as SINC, FIR filter will be a plus
• Good team player with strong interpersonal skills, both written and spoken.

工作條件

  • 工作經歷: 五年以上
  • 學歷要求: 碩士以上
  • 語文條件: 不拘
  • 其它條件: 未填寫

福利制度

◆ 員工認股
◆ 員工勞健保
◆ 三節禮金(品)
◆ 國定假日/週休二日
◆ 特休/年假
◆ 員工慶生
◆ 家庭日活動
◆ 交通費補助

更新日期:2021-12-01

應徵方式

  • 職務聯絡人: 陳小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年50%
3~5年0%
5~10年0%
10年以上50%
學歷分佈
碩士及以上100%
大學0%
專科0%
高中0%
高中以下0%
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