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台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
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廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

資深數位積體電路設計工程師/主管(Senior Digital ASIC Design Engineer/Manager)

  • 全職

As a digital ASIC Design Engineer, the individual’s primary responsibility will be RTL design.
This will include block/function definition, specification, design, simulation
and unit level verification of digital functions on Mixed Signal ASICs

Key Qualifications
• BSEE or MSEE with 5+ years of experience in front-end digital ASIC design.
• Proficient knowledge of industry standard tools and best practices for
RTL Design/simulation, Synthesis, timing constraints.
• Experience in design integration activities including Lint, CDC, ECO.
• Hands-on experience in at least one scripting language (Perl, Tcl, Python etc.)
• Understanding of Design Verification methodology. SystemVerilog/UVM a plus.
• Understanding of ASIC test methodology such as scan insertion, BIST and ATPG.
• Work with Physical design engineers to resolve physical, timing, power issues.
• Experience in hands-on lab evaluation and debugging activities.
• Experience in FPGA based prototyping a plus.
• Experience in image sensor/vision processor a plus.
• Good team player with strong interpersonal skills, both written and spoken.

工作條件

  • 工作經歷: 五年以上
  • 學歷要求: 碩士以上
  • 語文條件: 不拘
  • 其它條件: 未填寫

福利制度

◆ 員工認股
◆ 員工勞健保
◆ 三節禮金(品)
◆ 國定假日/週休二日
◆ 特休/年假
◆ 員工慶生
◆ 家庭日活動
◆ 交通費補助

更新日期:2021-12-01

應徵方式

  • 職務聯絡人: 陳小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

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學歷分佈
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