求職服務專線
台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
意見回饋
廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

Digital IC Verification (高級/資深工程師/經理)

  • 全職

Responsible for the creation and management of a design verification group
with ownership over various parts of a complex state-of-the-art SOC, from team building, to test planning, to test bench and test development, simulation and debugging, regression, documentation, coverage measurement, all the way to
tape out and post-silicon validation. Must be hands-on and able to act as a technical lead in addition to a manager.

The candidate should be a self-motivated, responsibility driven, team leader and player, willing to work hard for several years toward the eventual success of a startup company, and solve all the problems necessary in order to reach that
goal.

In addition to technical leadership, strong communication, planning, schedule
tracking and follow-up skills are required for team management.

The candidate will be offered a reasonable base pay, plus a generous grant of
stock options that has the potential of great financial reward in the future.

Management Knowledge and Experience Expected:
● Can communicate effectively in written and spoken English
● At least 1 year management experience of an ASIC design verification team
● Experience of a complete ASIC project from beginning to end, preferably as
manager
● Experience of hiring and firing
● Strong in team planning, communication, coordination, schedule tracking
and follow-up
● Problem reduction and solving
● Constant schedule optimization and recovery with the project goal in mind
at all times
● Can analyze and learn from feedbacks from supervisors, peers and
subordinates
● Takes responsibility and ownership seriously
● Can work effectively under stress
● Respect and appreciation for team members

工作條件

  • 接受身份: 上班族、應屆畢業生、原住民【相關法令】、二度就業、中壯齡(45~54歲)、中高齡(55~64歲)
  • 工作經歷: 不拘
  • 學歷要求: 碩士以上
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
  • 工作技能: 數位晶片產品開發、數位電路分析設計、數位電路驗證
  • 其它條件: ● ASIC design and verification processes and methodology
    ● RTL design architecture for ASIC, specifications, and testplanning
    ● RTL and testbench development using UVM methodology and
    SystemVerilog
    ● RTL and testbench simulation and debug using a waveform debugger
    ● Using commercial tools such as Synopsys and Cadence (continued)
    ● Device modeling and Verification IPs, and configuration, such as DDR,
    flash, PCIe, AXI
    ● Strong in programming languages such as C/C++/Perl/Python
    ● Bug tracking, regression and coverage measurement methodology
    ● Random testing
    ● Experience with emulator and FPGA is helpful
    ● Documentation and tracking for specs, plans, status and bugs

福利制度

法定項目

其他福利

員工激勵
1. 高競爭力的薪資水準
2. 保證年薪14個月
3. 每年調薪外加激勵獎金
4. 彈性上下班時間
5. 美式管理文化
6. 高額人才推薦獎金
7. 優於勞基法休假制度
8. 遠端上班制度健全

員工照顧
1. 年度免費健康檢查
2. 員工團體保險全額補助
3. 結婚禮金
4. 生育補助
5. 喪葬津貼

其他福利
1. 每月慶生下午茶會
2. 聖誕節禮物交換party
3. 年度尾牙
4. 員工聚餐
5. 提供免費餐飲小食
6. 免費汽機車停車位
7. 餐費補助

更新日期:2021-10-16

應徵方式

  • 職務聯絡人: 劉小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

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