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Principal Engineer, Mixed Signal Circuit Design

  • 全職

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity, and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

The high-quality clocking circuitry is the backbone of the high-speed mixed-signal IPs under development here in Infinera. You will have the great chance to demonstrate your creativity and superior technical competency by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient high-speed transmission.

Essential Functions and Key Responsibilities:
• Design, simulate, and verify the high frequency fractional-N PLLs;
• Architect, model, and simulation the noise accumulation and the skew of the clock distribution trees;
• Model, optimize, and measure the phase noise and jitter performance, and the skew of the whole clocking networks;
• Design and implement the high-frequency / low-noise VCOs;
• Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling;

Mandatory Knowledge/Skills/Abilities:
• Have good tracking records in designing low phase noise LC-VCO based PLLs to production;
• Abundant knowledge in the design trade-offs among different VCO topologies for MM-Wave applications, including but not limited to LC-VCO, TWO, SWO, etc.;
• Hands-on in designing the clock distribution network in Cadence environment;
• Good at modeling the phase noise and spurs of the frac-N PLLs;
• Possess extensive experience in designing and implementing the high frequency VCOs and clock trees with EMX tools;
• Have a decent understanding in CMOS analog / mixed signal design overall.

Preferred Knowledge/Skill/Abilities:
• Good at supervising testing activities;
• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail oriented;
• Has good interpersonal skills.

Education and Experience Requirements:
• M.S. in E.E. with 10+ years' experience, or Ph.D. in E.E. with 6+ years’ experience.

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.

工作條件

  • 工作經歷: 六年以上
  • 學歷要求: 碩士以上
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
  • 其它條件: 未填寫

福利制度

未填寫

更新日期:2022-01-21

應徵方式

  • 職務聯絡人: Miumiu
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內6-10人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年33%
5~10年0%
10年以上67%
學歷分佈
碩士及以上44%
大學33%
專科11%
高中0%
高中以下0%
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