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台北 02-2912-6104
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台中 04-3700-6104
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意見回饋

JR0161330 Analog Layout Engineer (Location: Malaysia)

  • 全職

To work on next generation with latest process technology of Intel, and work on next generation of mix-process node integration technology to enable various computing accelerator integration, in the era of hyper scale computing.
You will be responsible to deliver a good quality layout which includes the following:

Working with the circuit design team to plan and schedule work as needed to build a complex analog layout with Intel latest process nodes.

Running complete sets of design verification tools and completely understanding the LV, RV, ESD, DFM, and other reports.

Finding the fastest way to complete the layout that meets the stringent matching, performance area, and power requirements.

Implementing ECO and LCO to meet the design specification and having the ability to create schematics to debug issues/test cases.

On time delivery to the project schedule without compromise to the layout quality is always the top priority.


Soft skills or people skills are the personal attributes will be needed to succeed in the workplace. You will also be responsible to enhance your soft skills along the way.
This includes the following:

You are expected to participate in DDG self-development activities that allows you to enhance your communication such as listening and presentation skills.

You are also expected to be able to accept and apply feedback from others.

Work well with local teams or with other team cross-site.

工作條件

  • 接受身份: 上班族
  • 工作經歷: 五年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件: • Qualifications


    1. Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent.

    2. At least 5 years experience in deep SubMicron analog layout design.

    3. Experience building tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, pad IOs, ESD structures, etc.

    4. Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly.

    5. Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance.

    6. Experience with analog and DFM practices.

    7. High-level proficiency in interpretation of UNIX environment, Genesys, Calibre, DRC, ERC, LVS, etc. reports.

    8. Scripting experience in PERL, TCL, Unix or SKILL CODE is considered a plus.



    *Salary Range: RM 200K~250K (Malaysia)*

福利制度

In addition to a challenging and interesting work environment, Intel offers a benefits and compensation package that goes well beyond base salary. Below are some of our unique benefits and compensation programs. Please note that the benefits and compensation programs within Asia Pacific Sales and Marketing may vary somewhat as they are tailored to meet the needs of our employees in their own countries.

http://www.intel.com/jobs/apac/bencomp/

更新日期:2021-07-26

應徵方式

  • 職務聯絡人: Talent Acquisition
  • 聯絡E-Mail: 未填寫 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: Please directly send an English resume to Chew, Huey Shyan

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年33%
3~5年33%
5~10年0%
10年以上33%
學歷分佈
碩士及以上67%
大學33%
專科0%
高中0%
高中以下0%
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