求職服務專線
台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
意見回饋
廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

【2022 預聘研替】台灣_DTP Engineer

  • 全職

【本職缺僅接受台積電官方網站投遞】
請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://bit.ly/3hFIqAA

Description
At the beginning of new module research, IC design engineers and R&D engineers would cooperate closely with customers.
Therefore, once the new module technologies is developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time.
In TSMC, you could be exposed to the most advanced module technologies, provide solutions to partners in global IC design eco-system, and ensure the competitiveness in power, performance, and area.

【Physical Designer】
The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. Candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements.

【Standard Cell Eng.】
1.Path finding of library characterization for leading edge tech nodes
2.Support industrial standard library kits generation and QC
3.In-house library generation flow and/or utility development
4.RC parasitic extraction analysis and APR related analysis

【Layout Eng.】
IC layout for advanced technology(Std. cell/Memory/AMS/IO),
layout structure development for new technology,
pathfinding for new technology development,
customer engagement and layout support,
design and technology co-optimization(DTCO),
AI and automation for layout and physical design

【3DIC Eng.】
GPIO/ESD design, 3DIC/2.5DIC interface-IO design, and Si validation.

【System and Chip Design Solutions Development】
https://bit.ly/3lbCSzM

【FE design & DFT】
1.Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG)
2.Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc.
3. Technology benchmarking for PPA evaluation of the advanced nodes
4.DTCO (Design & Technology Co-Optimization) pathfinding and development

【SRAM Eng.】
1.SRAM design in 7nm/5nm/3nm for mobile, high performance computing, IoT, automotive applications.
2.RRAM/MRAM, emerging memory development
3. In memory computing research and development

【Design Flow/Methodology】
1. Advanced technology process design kits(PDK) and tech files(DRC, LVS, RC, ...) development and technical support
2. Advanced technology design development flow development and technical support
3. Automation program development to support design kits and flow development productivity/quality



Qualifications
1. Master degree in EE or CE
2. Good English speaking and writing capability
3. Good understanding of place and route flow
4. Good interpersonal and communication skills
5. Self-motivated and excellent team spirit

工作條件

  • 接受身份: 應屆畢業生、研發替代役
  • 工作經歷: 不拘
  • 學歷要求: 碩士
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件:

福利制度

詳見企業網站 http://www.tsmc.com/chinese/careers/compensation_benefits.htm

如欲投遞履歷,請上台積官網 http://www.tsmc.com/chinese/careers/index.htm

更新日期:2021-10-12

應徵方式

  • 職務聯絡人: 招募部
  • 聯絡E-Mail: 未填寫 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: 【本職缺僅接受台積電官方網站投遞】
    請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://bit.ly/3hFIqAA
    ===========================================
    若有任何疑問,請來信 tsmchr@tsmc.com (本信箱不接受履歷表),謝謝!
    ===========================================

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年100%
3~5年0%
5~10年0%
10年以上0%
學歷分佈
碩士及以上0%
大學100%
專科0%
高中0%
高中以下0%
一零四資訊科技享有網站內容著作權 © 2001- 2021 104 Corporation All Rights Reserved