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台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
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台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

Senior CPU Design Verification Engineer

  • 全職

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.

As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.

As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a random instruction test generator that produces self-checking direct test cases.

Responsibilities:

- Design, develop, documentation and deploy random instruction generator and
support multiple projects.
- Support execution of the generator and flows in the RTL design process.
- Integrate and ramp up on an existing instruction level verification flows.

工作條件

  • 接受身份: 上班族、應屆畢業生、外籍人士
  • 工作經歷: 三年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件: Requirements:
    - Master’s or PhD degree in Electrical Engineering, Computer Science or equivalent practical experience.
    - Familiar with CPU micro-architecture, memory sub-system and system software ( such as exception/interrupt handling, memory paging system.)
    - Familiar with baremetal/system software programming and Experience with creating direct test cases or porting microbenchmarks to measure system power or performance for design verification.
    - Basic understanding of Verilog, System-Verilog RTL, UVM and constrain random verification.
    - Experience with software project architecture/design and python/C++11 above programming.

福利制度

法定項目

其他福利

SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health benefits, employee stock option program, and much more.

In addition to these, we provide regional benefits including team-building events, annual physical examination, and education reimbursement for the employees in Taiwan.

We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you.

更新日期:2021-09-15

應徵方式

  • 職務聯絡人: Grace Chen
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: Please attach the latest English resume to your application. Thanks!

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