求職服務專線
台北 02-2912-6104 轉 2
   02-7703-3104 轉 2
意見回饋
廠商求才專線
台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
意見回饋

Design Verification Manager

  • 全職

1. Development of the verification infrastructure in UVM/System Verilog for block-level/chip-level design verification.
2. Create and maintain detailed test plans to ensure the quality and performance are met. Define and implement functional coverage, and enhance the test bench to ensure coverage closure.
3. Participate in design reviews and recommend improvements. Collaborate with ASIC and Firmware members to reproduce and debug functional errors in RTL models.
4. Lead a design verification team and manage verification project schedules, dependencies, and deliverables.

工作條件

  • 接受身份: 上班族、原住民【相關法令】、中壯齡(45~54歲)
  • 工作經歷: 五年以上
  • 學歷要求: 碩士以上
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
  • 其它條件: **Minimum**
    1. MS degree in Electrical Engineering, or equivalent with 5-10 years of experience including Verilog, System Verilog, UVM, ASIC Design Verification Flow. Relevant industrial experience preferred.
    2. Experience in writing shell, Perl, or Python scripts.
    3. Experience in writing C++/C.
    4. Good sense of debugging, reasoning, identifying the root cause of the problems.
    5. Excellent communication skills
    6. Positive thinking, good working attitude team player.

    **Plus requirement**
    1. Experience in SOC development flow is a plus.
    2. Knowledge of NAND flash devices and SSD is a plus.
    3. Knowledge of AMBA, PCIe, SATA/SAS, NVMe is a plus.

福利制度

法定項目

其他福利

◆ 獎金/禮品類
1.三節獎券/禮品
2. 專利獎金
3. 生日禮券
◆ 保險類
1.員工團保
2.眷屬團保
◆ 休閒類
1.每季部門聚餐
2.慶生會
3.員工旅遊
4. 每年定期舉辦員工健康檢查
◆ 制度類
1.伙食費
2.介紹獎金
◆ 請/休假制度
1.週休二日
2.優於勞基法特休/年假
3.不扣薪病假

更新日期:2021-10-05

應徵方式

  • 職務聯絡人: Joanne
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
目前無資料
學歷分佈
目前無資料
一零四資訊科技享有網站內容著作權 © 2001- 2021 104 Corporation All Rights Reserved