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台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
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Senior Design Engineer - Front End / DFT Implementation (Wireless)

  • 全職

Job Description:
• The Wireless Solutions Group (WSG) is seeking a Senior Design Engineer with Front End and DFT Implementation expertise to support IP/SOC development for our next generation, mixed signal, wireless products. The role will include driving and optimizing synthesis, implementing DFT circuits, power optimization, static timing analysis, and design verification using an industry leading SOC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.

Key Responsibilities:
• Candidate will provide hands on technical leadership to the WSG Silicon Development Team in the area of frontend and DFT design implementation.
• Drive and optimize Synthesis, Formal, DFT and STA for Microchip’s wireless SoC development.
• Drive DFT Integration Plan, Implementation and Verification (SCAN/ATPG/MBIST)
• Work closely with digital, analog, and physical design teams to optimize front-end (RTL-to-Netlist) implementation for performance, power, and area.
• Drive front-end low power implementation and optimization using UPF.
• Continuously improve RTL-to-Netlist tool flows and methodologies.
• Participate in Library and Memory IP selection (benchmarking/evaluations), characterization, and configuration.
• Interface with applications, product and test engineering, marketing, development systems, technology development, CAD, layout and other design organizations

工作條件

  • 接受身份: 上班族
  • 工作經歷: 三年以上
  • 學歷要求: 碩士以上
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
  • 其它條件: Desired Experience:
    • Participate in DFT Implementation and Verification
    • Participate in SoC development planning and scheduling.
    • Assist in the validation and debug silicon products in support of release to production.

    Required Skills:
    • Expertise in Synthesis, Formal Verification, and Static Timing Analysis, preferably with Synopsys tools.
    • Expertise in RTL coding and simulation using Verilog/SystemVerilog
    • Expertise in Design for Test, ATPG, MBIST preferably with Mentor Graphics /Tessent tools.
    • Knowledgeable in Chip level Design and Integration activities
    • Proficiency in common UNIX scripting languages (Perl, Python, Tcl, csh, etc.)
    • Familiarity with low-power implementation techniques (UPF).
    • Excellent debug skills in both functional and gate level simulations
    • Knowledge of revision control tools such as CVS, Perforce, Git
    • Experience working with cross functional global teams

    Desired Skills:
    • Knowledge of Programming Languages such as C++ or System C
    • Experience with Design for Test, ATPG
    • Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired
    • Solid Written and Verbal Communication skills in English

福利制度

-年度特休假優於勞基法
-全額補助團保(員工本人、配偶及子女)
-年度健康檢查補助
-婚喪喜慶及生育補助、三節禮金、生日禮金
-著重國際人才培訓,提供教育訓練方案,外訓課程補助
-Wellness Program

更新日期:2021-10-20

應徵方式

  • 職務聯絡人: 陳小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

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