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台北 02-2912-6104
   02-7703-3104
台中 04-3700-6104
上海 86-21-50277104 轉 1
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Systems Validation Engineer – SBIO FPGA

  • 全職

What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology.
This is an extraordinary opportunity to work in an outstanding company like AMD - Join us!

THE ROLE:
Candidate will be responsible for comprehensive electrical & functional test plans for the processor interface validation of processors. The candidate will execute electrical & functional test plans for client processors using FPGA hardware & software validation tools, oscilloscopes, & logic analyzers. Provide detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.

THE PERSON:
Requires good written and oral communication skills with a Demonstrated ability to communicate with a variety of engineering disciplines and management.

KEY RESPONSIBILITIES:
• pre silicon validation via FPGA for emulating the system
• post silicon validation, lab bring up and debug
• Root cause analysis and resolving system issues

PREFERRED EXPERIENCE:
• Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. Platform level experience with high speed I/O interfaces
• Experienced in FPGA development, Synthesis with logical & physical constraints, Timing closure and Place and Route in FPGA
• Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces.
• Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications.
• Requires good written and oral communication skills; Demonstrate the ability to communicate with a variety of engineering disciplines and management.

ACADEMIC CREDENTIALS:
B. S. in Electrical Engineering or Computer EngineeringUse the words preferred or desired, instead of required

LOCATION:
Taipei/Hsinchu, Taiwan

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law.

工作條件

  • 接受身份: 上班族
  • 工作經歷: 六年以上
  • 學歷要求: 大學以上
  • 語文條件: 英文 -- 聽 /精通、說 /精通、讀 /精通、寫 /精通
  • 其它條件: 未填寫

福利制度

獎金 / 禮品類
  1.年終獎金
  2.三節禮金/禮品
◆ 保險類
  1.勞保
  2.健保
  3.員工團保
  4.眷屬團保
  5.意外險
  6.職災保險
◆ 休閒類
  1.部門聚餐
◆ 制度類
  1.介紹獎金
  2.順暢的升遷管道
3.退休金、離職金制度
◆ 請 / 休假制度
  1.週休二日
  2.優於法定之特休/年假
  3.優於法定之陪產假
  4.不扣薪病假
  5.員工育嬰假
◆ 補助類
  1.員工停車位或停車補助
2.員工進修補助

更新日期:2021-10-21

應徵方式

  • 職務聯絡人: Ms. Chou
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年0%
5~10年0%
10年以上100%
學歷分佈
碩士及以上0%
大學50%
專科50%
高中0%
高中以下0%
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