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台北 02-2912-6104
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Design Rule (DR) Engineer, Staff (3020627)

  • 全職

【Responsibilities include】
* Lead, influence, and drive Qualcomm Asia Pacific VLSI design and enablement teams and our foundry suppliers across multiple sites and time zones to adopt design-to-yield and design-for-durability requirements.
* Evaluate process risk impact of new finfet process features and their design rules to IP/SOC VLSI designs concurrently with foundries. Generate viable execution workflows to mitigate potential yield impact. Collaborate with enablement teams or PnR teams for implementation.
* Author in-house design rules from Qualcomm experience and data, so we achieve a time-to-yield competitive advantage.
* Leverage design rules expertise to influence and drive adoption by multiple stakeholders, including but not limited to foundry customer engineers, PDK enablement/floorplan/PnR engineers, IP/SOC VLSI. Travel may be required up to once per quarter.

【Important attributes we look for】
* Creative, independent, and out-of-the-box thinker with strong problem-solving skills.
* Self-motivated, strong leadership and public speaking skills to influence internal and external stakeholders.
* Strong written and verbal communication skills to render complex issues with clarity allowing rational decisions.
* Excellent soft skills when interacting with cross-functional and cross-site teams, leveraging modern collaboration platforms for efficiency.

【Minimum Qualifications】

Master's, Electrical Engineering with 5+ years sub-10nm CMOS FinFet/DR/DFM/Yield-Management experience.

Required semiconductor experience in two of the following capacities:
* CMOS process integration engineer responsible for the qualification of CMOS technologies from development to production, or module integration engineer in lithography, etch, or CMP module.
* Yield enhancement engineer responsible for identifying the yield issue process or design root cause.
* DR/DFM engineer responsible for creating, maintaining, and applying design rules from early development to high volume production.
* Process test structure design and layout engineer translates above process risks into characterizable test keys where silicon data determine enhanced DR and DFM rules, guidelines, or workflows. Layout-dependent effects, parasitic effect, multi-patterning, and finfet technology familiarity required.
* Customer engineer guiding VLSI design teams through consulting or delivering clear application notes for yieldable designs.

【Preferred Qualifications】

Preferred: Doctorate, Electrical Engineering with 2+ years sub-10nm CMOS FinFet DR/DFM/Yield-Management experience.

* Foundry PDK use, application, and installation experience, including but not limited to Cadence tech file and map file setup, customization of foundry verification decks using Calibre Interactive.
* Project management skills and proficiency in organizing, hosting, and presenting complex technical material to a large multi-site design audience, remote/virtual or otherwise, in English. Effective use of modern collaboration platforms and co-authoring tools to drive efficiency, promote global teamwork is highly desirable. Hindi or Korean language skills desired.
* Extensive knowledge of analog sensitive/critical circuits (matching, symmetry, parasitic IR drop identification, PLL, ADC, DAC), especially in finfet matching or high voltage transistor stacking circuit techniques and methods.

【Education Requirements】

Required: Master's, Electrical Engineering, or equivalent experience.
Preferred: Doctorate, Electrical Engineering, or equivalent experience.

工作條件

  • 工作經歷: 五年以上
  • 學歷要求: 碩士以上
  • 語文條件: 不拘
  • 其它條件: 未填寫

福利制度

Along with quality, life-enhancing programs. When we say the benefits of working at Qualcomm are many, you’ll see we mean that quite literally. Just take a look…

The benefits listed below apply to the employees of Qualcomm Taiwan Corporation & Qualcomm Communication Technologies Limited located in Taiwan

National Health and Labor Insurance
National Retirement Scheme
Public Holidays
Paid Maternity Leave
Paid Paternity Leave
Annual Leave
Education Assistance

更新日期:2022-01-21

應徵方式

  • 職務聯絡人: HR
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽
  • 它: Please kindly apply via website:
    https://qualcomm.wd5.myworkdayjobs.com/External/job/Hsinchu-City/Design-Rule--DR--Engineer--Staff_3020627

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年0%
5~10年0%
10年以上100%
學歷分佈
碩士及以上0%
大學100%
專科0%
高中0%
高中以下0%
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