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Design Engineer - DFT (Wireless)

  • 全職

Job Description:
In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless
SoC Development. Your scope of work includes but not limited to:
• Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools
for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan.
• Work closely with front-end team to ensure the logic structures permit and are suitable for DFT insertion.
• Work closely with front-end and back end implementation team to ensure that DFT
implementation does not impact the functionality and timing of the chip
• Develop timing constraint (SDC) files for DFT modes and corners
• Work with Frontend Team to close timing in DFT modes
• Perform RTL/Gate-level simulation to ensure the post-layout design passed the DFT test benches
• Prepare and Debug DFT test patterns for production team
• Develop DFT methodology to improve test coverage and cost
• Perform DFT sign-off checklist and reviews

Key Responsibilities:
• Candidate will provide hands on technical leadership to the WSG Silicon Development Team in the area of DFT implementation.
• Drive DFT Integration Plan, Implementation and Verification (SCAN/ATPG/MBIST)
• Continuously improve DFT flows and methodologies.
• Assist in the validation and debug silicon products in support of release to production.
• Interface with product and test engineering, technology development, CAD, layout and other design organizations

工作條件

  • 接受身份: 應屆畢業生
  • 工作經歷: 不拘
  • 學歷要求: 大學 碩士
  • 語文條件: 英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
  • 其它條件: Desired Experience:
    • Familiar with Digital IC Design Flow
    • Familiar with Scan/MBIST Insertion and Verification flow
    • Experience working with cross functional global teams


    Required Skills:
    • Expertise in Design for Test, ATPG, MBIST preferably with Mentor Graphics /Tessent tools.
    • Familiarity with Scan Insertion (DFT Compiler), Formal Verification, and Static Timing Analysis
    • Familiarity with Verilog, Verilog simulation, and debug.
    • Familiarity with Tcl, Perl, Python, and Shell scripting.
    • Solid understanding of digital implementation tools and flow
    • Experience with advance technology nodes (55nm and below).
    • Good Communication and teamwork skills


    Desired Skills:
    • Knowledge and exposure to complete Silicon Tapeout flow is desired
    • English Language proficiency is desired

    Other:
    • We are looking for candidates who are self-motivators, energetic, and team players. Candidates will need to do some light travel to support the global wireless team.

福利制度

-年度特休假優於勞基法
-全額補助團保(員工本人、配偶及子女)
-年度健康檢查補助
-婚喪喜慶及生育補助、三節禮金、生日禮金
-著重國際人才培訓,提供教育訓練方案,外訓課程補助
-Wellness Program

更新日期:2021-11-22

應徵方式

  • 職務聯絡人: 陳小姐
  • 聯絡E-Mail: (請利用104履歷表應徵此工作) 我要應徵
  • 洽: 不接受電洽
  • 洽: 不接受親洽

應徵分析

兩週內0-5人應徵
經歷分佈
新鮮人0%
1~3年0%
3~5年100%
5~10年0%
10年以上0%
學歷分佈
碩士及以上100%
大學0%
專科0%
高中0%
高中以下0%
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