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Design Verification Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
- Make a Functional Test Plan about SoC Design - Make a Test Plan of Constrained Random Verification Test and Directed Test - Verification Environment Setup - Design Verification to meet the Functional Coverage and the Code coverage - Design Verification based on various Level of design (IP / Sub-system, SoC Level)
一週以前更新 兩週內0-5人應徵
2021-11-26

High Speed IP Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
- High Speed Interface IP and Subsystem Design - IP configuration and IP level verification - Subsystem Design including Link, PHY and Sub-controller - Subsystem Verification and Bring-up - Subsystem Level Sanity Check : Lint, CDC, Synthesis - Subsystem level SDC generation and verification (PT constraint) - Subsystem level UPF generation and verification (VC LP) - Performance Profiling, and Power
一週以前更新 兩週內0-5人應徵
2021-11-26

SOC Design Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
- Determination of IP Design-Specification and Architecture - Development of Sub-Block Level - Logic Design and Verification - Block Level Sanity Check : Lint, CDC, Synthesis, EQ, ECO - Block level SDC generation and verification (PT constraint) - Block level UPF generation and verification (VC LP) - Performance Profiling, Power Estimation
一週以前更新 兩週內0-5人應徵
2021-11-26

SOC Design Tech. Leader

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
- Determination of SoC Design-Specification and Development of Top level Architecture - Logic Design and Verification - Architecture Design of BUS and POWER - TOP Level Sanity Check : Lint, CDC, Synthesis, EQ, ECO - TOP level & Block level SDC generation and verification (PT constraint) - TOP level & Block level UPF generation and verification (VC LP) - Performance Profiling, Power Estimation - Su
一週以前更新 兩週內0-5人應徵
2021-11-26

R&D Assistant

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 月薪 35,000 元以上
1. 研發文件管理與翻譯 2. 研發專案統管理 3. 協助研發部門處理相關行政作業 4. 主管交辦事務
一個月以前更新 兩週內0-5人應徵
2021-11-02

Physical Design Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR Implementation. - floorplan, placement, clock tree synthesis - routing, timing optimization. 2. Physical verification. (DRC/LVS) 3. Timing Closure. - STA - PT, Tweaker 4. Power analysis and fixing (IR/EM). 5. Low power implementation. - UPF flow
一個月以前更新 兩週內0-5人應徵
2021-11-02

Frontend Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 月薪 50,000 元以上
(1) Timing Closure Fixing (2) DFT expert (SCAN/ATPG/ MBIST/BSCAN/MBISR/At-Speed) (3) Hierarchical Experience is preferred for 100M+ gate count (4) CAD tool evaluation and consultant for frontend implementation
一個月以前更新 兩週內0-5人應徵
2021-11-02

Senior Frontend Engineer (Synthesis)

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) Ongoing project R2G synthesis (top down/button up) (2) Logic equivalent check with R2G/G2G (3) Pre netlist timing closure (4) Synthesis flow maintenance
一個月以前更新 兩週內0-5人應徵
2021-11-02

Project Leader

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 八年以上工作經驗
  • 待遇面議
- Coordinate internal resources and third parties/vendors for the flawless execution of projects - Ensure that all projects are delivered on-time, within scope and budget - Ensure availability and allocation of resource - Develop a detailed project plan to monitor and track progress - Manage changes to the project scope, project schedule and project costs based on appropriate verification techniqu
一個月以前更新 兩週內0-5人應徵
2021-11-02

Senior Frontend Engineer (STA)

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) SDC validation and perform STA (2) Advance STA signoff flow, domain knowledge enhancement (3) Timing closure with APR engineer (4) Review clock structure and Adjust clock tree for timing fixing
一個月以前更新 兩週內0-5人應徵
2021-11-02

Low Power Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
- UPF construct - Pre power structure implement (Using DC) - Pre/Post power signoff check - Low power flow maintenance
一個月以前更新 兩週內0-5人應徵
2021-11-02

Design Methodology Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) Responsible for in-house methodology development to improve or verify implementation quality. (2) Tool evaluation and support project implementation.
一個月以前更新 兩週內0-5人應徵
2021-11-02

Design manager_Standard Cell

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 八年以上工作經驗
  • 待遇面議
1. Conduct standard cell library projects and lead design team. 2. Develop standard cell design methodology to ensure mass-production quality 3. Standard cell circuit design, analysis, characterization 4. Optimize circuit/layout
一個月以前更新 兩週內0-5人應徵
2021-11-02

DFT Implementation Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT planning & implementation for MBIST/SCAN/ATPG/BSCAN... (2) Perform STA & timing closure for DFT modes. (3) Create DFT test pattern & perform DFT Verilog simulation. (4) Co-work with Test Engineers to bring-up testing in ATE.
一個月以前更新 兩週內0-5人應徵
2021-11-02

DFT CAD Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT design methodology development. (2) Flow development for MBIST, SCAN & ATPG. (3) In-house DFT design-kit/utility/script development.
一個月以前更新 兩週內0-5人應徵
2021-11-02
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