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13 筆查詢結果

(Sr.) Test Engineer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
He/She shall interface with design engineer, product engineer, 3rd party test vendors and manufacturing sites. The scope of work includes but is not limited to: • To develop the test program for high-volume manufacturing ICs test on Teradyne J750 and Chroma ATE platform. • To design test hardware e.g load board, probe card and reliability (HTOL, THB, etc) boards. • Post-silicon debug, characteri
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1.Gb Ethernet PHY IP Development on 0.13um Process 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library
1天以前更新 兩週內0-5人應徵
2021-12-07

Business Development

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
The Business Development will be responsible for the overall management of the Company’s business development organization. Responsibilities: • Serve as a key member of the executive team that sets the company’s strategic direction. • Spearhead business development and marketing initiatives that are consistent with the company’s overall strategy. • Manage multiple business initiatives in a s
1天以前更新 兩週內6-10人應徵
2021-12-07

International Sales

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 大學 碩士
  • 五年以上工作經驗
  • 待遇面議
1.The candidate is to be responsible for achieving the sales revenue target assigned and he/she is expected to be proficient in sales account. 2. To be responsible for sales includes A. System solution sales i. SPG101 chip sales ii. Mcard, Mdrive iii.AI chip sales iv.Medical AI product sales B. ASIC design sales
1天以前更新 兩週內0-5人應徵
2021-12-07

Director of Sales

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
Responsible for planning and implementing sales and marketing activities in order to meet company targets for retention growth and profitability. •Responsible for the sales of our products (IOT Connectors) into the medical equipment, connected cars, Industry 4.0 and Smart home appliances. •Meet or exceed agreed sales target. •Responsible to build a strong sales team by recruiting, managing,
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, fun
1天以前更新 兩週內0-5人應徵
2021-12-07

SoC/ASIC/IP digital design engineer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
- Design/development of SoC subsystem blocks. - Responsible for SOC system Integration/Verification - Generate detailed micro-architecture technical specifications and systems requirements and deliver the design - Work closely with verification team to develop verification plans and actively participate in debug phase - Work hands-on and own their design through the full SoC/ASIC development p
1天以前更新 兩週內0-5人應徵
2021-12-07

Sr. Analog Design Engineer/Manager

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
-Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. -Experience in analog IP development that include ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies.
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
A. Familiar with Standard Cell Circuit Design, verification of functionality, performance and power improvement methodology. B. Calculate cost( tools and man power ) of developing full set standard cell libraries C. Be able to judge and select required cells for target standard cell libraries D. Capable of defining timing specification for target standard cell libraries E. Plan and evaluate the R
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士以上
  • 六年以上工作經驗
  • 待遇面議
1.0.13um & 0.18um ASIC Memory cell and Memory Compiler Development 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library
1天以前更新 兩週內0-5人應徵
2021-12-07

DDR PHY Designer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1.Responsible for the logic and circuit design of the physical interface to DDR3 DRAM 2.Work with layout and pad designer to ensure the interface running at high frequency 3.Work with verification engineer on testing the DDR DRAM interface 4.Work with system engineer in bringing up the DDR DRAM interface to high frequency 5.Responsible for debugging any DDR DRAM issue on the chip
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Et
1天以前更新 兩週內0-5人應徵
2021-12-07
佳易科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Gb Ethernet Controller IP Development on 0.13um Technology 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library
1天以前更新 兩週內0-5人應徵
2021-12-07
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