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數位IC設計工程師 軟體設計工程師 類比IC設計工程師的工作機會

53 筆查詢結果
創意電子股份有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
職缺1 - Chip Application Front-End Engineer ※Job Contents: 1. Timing closure. 職缺2 - DFT Design Engineer ※Job Contents: 1. DFT Planning of MBIST/SCAN for whole chip. 職缺3 - APR Engineer ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. ※ 歡迎新鮮人投遞履歷 ※ ※ 指導者引導帶領 ※ ※ 先進製程技術相關專
5天以前更新 兩週內11-30人應徵
2021-09-13

Software Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. IP verification for SOC integration 2. IP driver porting/coding on Linux/RTOS ※Requirements: 1.碩士以上,電機電子/資工系所佳 2.Experience on Ethernet IP driver and network software stack porting/development 3.Experience on U-Boot and Linux porting to a new SoC
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Develop 2.5D/3D-IC multi-die stacking design flow for TSMC CoWoS, InFO, SoIC advanced technology 2. Deploy and enhance 2.5D/3D-IC physical design flow in real design with performing 3D multi-die stacking tasks: die-stacking configuration, floorplanning, layout, and die-to-die auto-routing 3. Develop 2.5D/3D-IC extraction signoff flow to ensure signal and power integrity 4. Design
5天以前更新 兩週內6-10人應徵
2021-09-13

數位IC設計工程師

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. 參與 SOC 或 Subsystem 設計/整合,驗證開發。 2. 參與 SCU 設計/整合,驗證開發。 3. 需跨部門合作如軟體驗證,量產程式開發。 ※Requirements: 1. 語言: Verilog, systemverilog, familiar with C/TCL/Perl/makefile is plus. 2. 設計流程: Synthesis/Constraint/STA, CDC flow. 3. Knowledge: AMBA protocol, verification method(ex. UVM).
5天以前更新 兩週內0-5人應徵
2021-09-13
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
GUC Mixed Signal Department ●符合以下經驗之一 1. PLL/DLL/VCO circuit desgin 2. ADC circuit design 3. DAC circuit design 4. High Speed SerDes circuit design 5. 熟Matlab佳 6. 熟mixed signal design flow佳(ex. Inductor extraction, RC extraction, mixed mode simulation) 自我推薦獎金辦法: 1.期間限定:即日起至2021/09/30止 2.適用職缺: 職缺上有註明”享自我推薦獎金,獎金最高15萬”者適用 3.獎勵內容: 相關年資1
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Location:台北/新竹 2. Perform Netlist-to-GDS Physical implementation. 3. Perform STA timing closure. 4. Perform physical verification, including DRC/LVS/IR and DFM analysis ※Requirements: 1. 電子、電機、資工相關科系畢業 2. 大學畢可,碩士佳 3. 有EDI/ICC經驗者佳 4. SOC/ASIC concept is a must 5. 具學習意願,願意接受公司培訓
5天以前更新 兩週內6-10人應徵
2021-09-13

AI/ML EDA Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1. Responsible for RTL to GDSII design flow development and automation with machine learning technique. 2. Project support/execution & collaboration with EDA vendors and academic. 3. Design flow/scripts/environment development for advanced process nodes. ※Requirements: 1. Experience in EDA design flow 2. Knowledge with script and programming (TCL/Perl/...) skills 3. Knowledge with
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. DFT Planning of MBIST/SCAN for whole chip. 2. Implement of MBIST and SCAN 3. Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check 4. Discuss with Test Engineers to provide solutions to DFT testing ※Requirements: 1. Graduated in EE or related Engineering 2. Proficient in programming skill and UNIX shell. 3. Compression / Share code / Ultra flow implemen
5天以前更新 兩週內0-5人應徵
2021-09-13
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
(一)工作內容: 1. Ramp up high-speed interface protocol, execute test plan 2. In charge of Subsystem DV for SPEC-IN Project 3. In charge of Emulation flow 4. Functional verification with Palladium Z1 ※工作地點為新竹。 (二)需求條件: 1.Degree in EE or CS Engineering, MS required 2.Excellent analytical and problem solving skills ※請同學附上論文/研究作品和成績單。
5天以前更新 兩週內0-5人應徵
2021-09-13
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Job Descriptions: 1. ARM leading edge CPU integration 2. Testbench build up 3. CPU subsystem spec study, architecting and performance analysis, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. Job Requirements: 1.Familiar with ARM V8 CPU and AMBA architecture 2.Familiar with synopsys VIP and verification methodology 3.Good at digital IC front-end design flow such as Ve
5天以前更新 兩週內0-5人應徵
2021-09-13

Design Verification Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.數位IC (RTL code) 驗證。 2.建立測試計畫,按計畫建立隨機測試向量。 3.與Design Team密切合作改善測試品質,達成function coverage/code coverage sign off要求。 ※Requirements: 1.Experience with 物件導向程式設計/UVM based environment building is a plus。 2.學歷:大學以上,資工/電機電子相關科系畢。 3.工作經驗:不拘。 4.擅長工具:Verilog , SystemVerilog ,C/C++。
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 1.Develop power and IR verification methodology to ensure chip power integrity. 2.Perform IR verification, including power calculation, IR drop and EM analysis, and library power modeling. 3.Develop design flow to analyze the quality of power delivery network, including power grid, bump assignment, and chip-package co-design. 4.Support power network improvement. Job Requirements
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took responsibility of planning low-power structure and review flow (CPF/UPF). 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar
5天以前更新 兩週內6-10人應徵
2021-09-13
創意電子股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱 Physical Design Technical Manager (APR) ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Com
5天以前更新 兩週內0-5人應徵
2021-09-13

DFT EDA Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Responsible for IC DFT design methodology development and project support. 2. Flow development for Memory BIST, Scan, Boundary Scan, ATPG and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in DFT flow development (Memory BIST/BISR, SCAN, Boundary Scan, ATPG, Logic BIST, etc) 3. Experience in low power flow
5天以前更新 兩週內0-5人應徵
2021-09-13
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