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數位IC設計工程師 類比IC設計工程師的工作機會

49 筆查詢結果
創意電子股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1. PCIe PCS and PHY digital design
4天以前更新 兩週內0-5人應徵
2021-07-27
創意電子股份有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
職缺1 - Chip Application Front-End Engineer ※Job Contents: 1. Timing closure. 職缺2 - DFT Design Engineer ※Job Contents: 1. DFT Planning of MBIST/SCAN for whole chip. 職缺3 - APR Engineer ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. ※ 歡迎新鮮人投遞履歷 ※ ※ 指導者引導帶領 ※ ※ 先進製程技術相關專
5天以前更新 兩週內11-30人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
GUC Mixed Signal Department ●符合以下經驗之一 1. PLL/DLL/VCO circuit desgin 2. ADC circuit design 3. DAC circuit design 4. High Speed SerDes circuit design 5. 熟Matlab佳 6. 熟mixed signal design flow佳(ex. Inductor extraction, RC extraction, mixed mode simulation) 自我推薦獎金辦法: 1.期間限定:即日起至2021/09/30止 2.適用職缺: 職缺上有註明”享自我推薦獎金,獎金最高15萬”者適用 3.獎勵內容: 相關年資1
5天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Location:台北/新竹 2. Perform Netlist-to-GDS Physical implementation. 3. Perform STA timing closure. 4. Perform physical verification, including DRC/LVS/IR and DFM analysis ※Requirements: 1. 電子、電機、資工相關科系畢業 2. 大學畢可,碩士佳 3. 有EDI/ICC經驗者佳 4. SOC/ASIC concept is a must 5. 具學習意願,願意接受公司培訓
5天以前更新 兩週內11-30人應徵
2021-07-26

Design Verification Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.數位IC (RTL code) 驗證。 2.建立測試計畫,按計畫建立隨機測試向量。 3.與Design Team密切合作改善測試品質,達成function coverage/code coverage sign off要求。 ※Requirements: 1.Experience with 物件導向程式設計/UVM based environment building is a plus。 2.學歷:大學以上,資工/電機電子相關科系畢。 3.工作經驗:不拘。 4.擅長工具:Verilog , SystemVerilog ,C/C++。
5天以前更新 兩週內6-10人應徵
2021-07-26

IP Technical Project Manager

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
[Responsibilities] 1.Work closely with all IP (R&D) engineering teams to provide support for all activities in the product development and customer support. 2.With coordination with IP (R&D) teams, communicate and work with customer. 3.To support customer engagement and work with sales for IP promotion. 4.To management IP product documents. [Skills & Qualifications] 1.Degree in Engineering
5天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱 Physical Design Technical Manager (APR) ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2, Innovus w
5天以前更新 兩週內6-10人應徵
2021-07-26

AI/ML EDA Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1. Responsible for RTL to GDSII design flow development and automation with machine learning technique. 2. Project support/execution & collaboration with EDA vendors and academic. 3. Design flow/scripts/environment development for advanced process nodes. ※Requirements: 1. Experience in EDA design flow 2. Knowledge with script and programming (TCL/Perl/...) skills 3. Knowledge with
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1. 工作地點:Hsinchu 2. Responsible for ASIC tech activities of pre-sale projects, including tech capability promotion, Effective communication with clients for tech and business needs, tech proposal delivery and SOW drafting. 3. Handle ASIC program management and key issue resolving from Netlist-in to Mass production. 4. Business travel is expected. ※Requirements: 1. 10~15 year
5天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
DFT Technical Manager ※Job Contents: 1.工作地點:台南 2.Communicate with customers to provide suitable test architecture planning for production. 3.Communicate with external teams to keep track of issues and progress. 4.Managing schedules and supporting cross-functional engineering effort. 5.Assist DFT structure implementation and review team members' work. 6.Working with test engineers to bring
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
Job description: a. Cell library and foundry process technology file management b. Technical support for standard cell and technology file related issues c. Circuit simulation and characterization d. Cell optimization for power and performance Nice to have: 1. Experience in cell library or circuit design 2. Advanced process (N16 and beyond) cell timing / power modeling experience is plus 3. Has
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Follow customer design requirement to design the customized DDR, PCIE, USB and other Subsystem IPs for SoC chip-level integration 2. IP Wrapper Design, Testing Circuit Design, Implementation, Verification and Manufacturing 3. IP Subsystem Package Deliverable Enhancement 4. EDA and Automation Flow Development ※Requirements: 1. MS/PhD EE or CS related departments 2. 5 years or
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. Package/PCB Model extraction by EM tooling. 2. Whole system level signal/power integrity modeling, characterization and simulations including PCB, package and chip IOs. 3. Silicon chip results correlation with simulation 4. Co-simulation flow development 5. Co-work with IC designer to define specification and solve the silicon related signal and power integrity problems in the s
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 1.Develop power and IR verification methodology to ensure chip power integrity. 2.Perform IR verification, including power calculation, IR drop and EM analysis, and library power modeling. 3.Develop design flow to analyze the quality of power delivery network, including power grid, bump assignment, and chip-package co-design. 4.Support power network improvement. Job Requirements
5天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 專科以上
  • 四年以上工作經驗
  • 待遇面議
※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took respoinsibility of planing low-power structure and review flow(CPF/UPF) 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar wi
5天以前更新 兩週內0-5人應徵
2021-07-26
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