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數位IC設計工程師 IC佈局工程師的工作機會

50 筆查詢結果

Front-End Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 主要負責TSMC先進製程從RTL to GDS Design Chip Implementation的前端設計包括靜態時序分析&優化 1. Timing constraint check 2. Static timing analysis using Synopsys PrimeTime 3. Low power design verification using CPF/UPF 4. Power analysis using PrimeTime PX 4. IP QA (quality assurance) and verification 5. Standard cell, IP, memory library and techfile maintenance 6. IO pin sequence assig
4天以前更新 兩週內6-10人應徵
2021-10-12
創意電子股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱 Physical Design Technical Manager (APR) ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Com
4天以前更新 兩週內0-5人應徵
2021-10-12
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Location:台北/新竹 2. Perform Netlist-to-GDS Physical implementation. 3. Perform STA timing closure. 4. Perform physical verification, including DRC/LVS/IR and DFM analysis ※Requirements: 1. 電子、電機、資工相關科系畢業 2. 大學畢可,碩士佳 3. 有EDI/ICC經驗者佳 4. SOC/ASIC concept is a must 5. 具學習意願,願意接受公司培訓
4天以前更新 兩週內6-10人應徵
2021-10-12

Layout Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 專科 大學
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1.Mix mode 2.Analog layout 3.Full Customer Layout ※Requirements: 1.具類比IP、special I/O、Mixed mode full custom layout經驗。 2.具full custom IC layout / verification經驗。 3.具 Laker/Virtuoso, Calibre LVS / DRC/ Calibre等工具經驗。 4.具16/ 7/5nm IC layout experiences is a plus. 5.歡迎有IC layout經驗3年以上者加入。
4天以前更新 兩週內6-10人應徵
2021-10-12
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
DFT Technical Manager ※Job Contents: 1.工作地點:台南 2.Communicate with customers to provide suitable test architecture planning for production. 3.Communicate with external teams to keep track of issues and progress. 4.Managing schedules and supporting cross-functional engineering effort. 5.Assist DFT structure implementation and review team members' work. 6.Working with test engineers to bring
4天以前更新 兩週內0-5人應徵
2021-10-12
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
(一)工作內容: 1. Ramp up high-speed interface protocol, execute test plan 2. In charge of Subsystem DV for SPEC-IN Project 3. In charge of Emulation flow 4. Functional verification with Palladium Z1 ※工作地點為新竹。 (二)需求條件: 1.Degree in EE or CS Engineering, MS required 2.Excellent analytical and problem solving skills ※請同學附上論文/研究作品和成績單。
4天以前更新 兩週內6-10人應徵
2021-10-12
創意電子股份有限公司
  • 專科 大學
  • 一年以上工作經驗
  • 待遇面議
歡迎具有1年以上 IC layout 經驗者加入,本公司提供完整教育訓練;若派駐者,除保障年薪14個月、分紅與員工持股信託外,並享有高額派駐津貼與福利!!歡迎加入高階製程的行列!! ※Job Contents: 1.Mix mode 2.Analog layout 3.Full Customer Layout 4.SRAM/TCAM ... etc memory IC layout ※Requirements: 1.具類比IP、special I/O、Mixed Mode full custom layout 經驗。 2.具full custom IC layout / verification 經驗。 3.具 lak
4天以前更新 兩週內11-30人應徵
2021-10-12
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Front-End EDA Engineer ※Job Contents: 1. Responsible for IC front-end design methodology development and project support. 2. Flow development for lint, constraint check, synthesis, STA, power analysis and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in R2N flow development (lint/constraint check/synthesis/STA/Simulation/f
4天以前更新 兩週內0-5人應徵
2021-10-12
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. ※請同學附上論文/研
4天以前更新 兩週內0-5人應徵
2021-10-12

DFT EDA Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Responsible for IC DFT design methodology development and project support. 2. Flow development for Memory BIST, Scan, Boundary Scan, ATPG and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in DFT flow development (Memory BIST/BISR, SCAN, Boundary Scan, ATPG, Logic BIST, etc) 3. Experience in low power flow
4天以前更新 兩週內6-10人應徵
2021-10-12
創意電子股份有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
職缺1 - Chip Application Front-End Engineer ※Job Contents: 1. Timing closure. 職缺2 - DFT Design Engineer ※Job Contents: 1. DFT Planning of MBIST/SCAN for whole chip. 職缺3 - APR Engineer ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. ※ 歡迎新鮮人投遞履歷 ※ ※ 指導者引導帶領 ※ ※ 先進製程技術相關專
4天以前更新 兩週內11-30人應徵
2021-10-12
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Develop 2.5D/3D-IC multi-die stacking design flow for TSMC CoWoS, InFO, SoIC advanced technology 2. Deploy and enhance 2.5D/3D-IC physical design flow in real design with performing 3D multi-die stacking tasks: die-stacking configuration, floorplanning, layout, and die-to-die auto-routing 3. Develop 2.5D/3D-IC extraction signoff flow to ensure signal and power integrity 4. Design
4天以前更新 兩週內0-5人應徵
2021-10-12
創意電子股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1. 工作地點:Hsinchu 2. Responsible for ASIC tech activities of pre-sale projects, including tech capability promotion, Effective communication with clients for tech and business needs, tech proposal delivery and SOW drafting. 3. Handle ASIC program management and key issue resolving from Netlist-in to Mass production. 4. Business travel is expected. ※Requirements: 1. 10~15 year
4天以前更新 兩週內0-5人應徵
2021-10-12
創意電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took responsibility of planning low-power structure and review flow (CPF/UPF). 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar
4天以前更新 兩週內6-10人應徵
2021-10-12

AI/ML EDA Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1. Responsible for RTL to GDSII design flow development and automation with machine learning technique. 2. Project support/execution & collaboration with EDA vendors and academic. 3. Design flow/scripts/environment development for advanced process nodes. ※Requirements: 1. Experience in EDA design flow 2. Knowledge with script and programming (TCL/Perl/...) skills 3. Knowledge with
4天以前更新 兩週內6-10人應徵
2021-10-12
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