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安霸股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1.VLSI Physical Design 2.Executing floorplanning, design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3.Tapeout with multi-million gates count SOC design on leading edge technologies. 4.Develop physical design flows/solutions on the latest cutting edge technology node.
4天以前更新 兩週內0-5人應徵
2021-11-25

APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 3.Requirement: 3-1. Familiar with ASIC design flow相關尤佳 3-2. Hands on APR physical design from netlist to DRC/LVS tapeout experience is required 3-3. Familiar with hierarchical and/or low power design flow相關尤佳
兩週以前更新 兩週內11-30人應徵
2021-11-15

Physical Design Engineer APR

FULL_TIME
新竹市
104獵才顧問_一零四資訊科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.
一週以前更新 兩週內0-5人應徵
2021-11-21

Physical Design/APR Manager/Engineer

FULL_TIME
新竹縣竹北市
芯偉有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
CAD/APR Engineer : 1) IC Digital Design Physical APR. 2) Including Library preparation, floor planning, timing closure 3) Build up the IC design flow 4) Familiar with Tcl/Shell/Perl/makefile 5) Interesting in power analysis / backend cad flow creation 6) Familiar with Digital & Analog Design flow
三週以前更新 兩週內0-5人應徵
2021-10-31

資深APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Physical design of multi-million instance-count SOC project. Physical design activities include floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. (APR Support) 2.Build advanced physical design methodology to facilitate UDSM design project for timing/power/DFM closure and CPU/GPU hardening. 3.Requirement: 3-1. Familiar with Cadence EDI Platform and/or Syno
兩週以前更新 兩週內0-5人應徵
2021-11-15
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis, routing and Tape-out sign off. 2. Familiar IP & Testchip APR flow develoment. 3. Support STA timing analysis and fixing. 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. 6. Familiar with APR tools (Cadence Innovus or Synopsys ICC2.) 7
一週以前更新 兩週內0-5人應徵
2021-11-22

APR Physical Design工程師

FULL_TIME
新竹縣竹北市
香港商鑫澤數碼股份有限公司台灣分公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1.Perform Netlist-to-GDS design flow of SOC chip/SYS/Block. 2.TOP level floorplan, block partition, block integration, timing closure and tapeout. 3.Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4.High speed IP implementation, DDR, GPU, CPU.
4天以前更新 兩週內0-5人應徵
2021-11-25
力智電子股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
APR
兩週以前更新 兩週內0-5人應徵
2021-11-10

Physical Design APR Engineer

FULL_TIME
新竹縣竹北市
M31 Technology Corporation_円星科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop analysis. 4. Familiar with Synopsys ICC/ ICC2 or Cadence Innovus 5. tcl or perl script language skill is preferred.
6天以前更新 兩週內0-5人應徵
2021-11-23

APR Physical Design工程師

FULL_TIME
新竹市
聯發科技集團_達發科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. Requirement: a) Hands on whole chip APR physical design from netlist to DRC/LVS tapeout b) Familiar with Cadence Innovus & Synopsys ICC experience is required
一週以前更新 兩週內6-10人應徵
2021-11-22
美商賽發馥股份有限公司臺灣分公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs. As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices. Industry-leading innovators
5天以前更新 兩週內0-5人應徵
2021-11-24
天鈺科技股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
Develop physical design methodology and implementation.
兩個月以前更新 兩週內0-5人應徵
2021-09-03
神盾股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
工作內容: Physical design APR from netlist to DRC/LVS tape-out, including floorplan, power plan, physical synthesis, clock tree synthesis, routing.
兩個月以前更新 兩週內0-5人應徵
2021-09-10
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
兩週以前更新 兩週內0-5人應徵
2021-11-15

Physical Design Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR Implementation. - floorplan, placement, clock tree synthesis - routing, timing optimization. 2. Physical verification. (DRC/LVS) 3. Timing Closure. - STA - PT, Tweaker 4. Power analysis and fixing (IR/EM). 5. Low power implementation. - UPF flow
三週以前更新 兩週內0-5人應徵
2021-11-02
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