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Senior analog/IC design engineer

FULL_TIME
新竹縣竹北市
香港商芯視達有限公司台灣辦事處
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Highspeed circuit design,simulation and verificatin such as transmitter/receiver/pll/cdr in MIPI C/D/M-PHY etc, and related test board design support 2. Guide layout engineer to complete and optimize the layout 3. Test & debug for product
一個月以前更新 兩週內0-5人應徵
2021-12-23

Senior Analog Hardware Design Engineer

FULL_TIME
新竹縣竹北市
美商艾科斯羅國際股份有限公司台灣分公司
  • 大學以上
  • 五年以上工作經驗
  • 月薪 40,000 元以上
Job Summary: This position is for a senior hardware design engineer reporting into the Digital/Mixed Signal product development group. The successful candidate will be leading the development of high-performance analog/mixed signal technology as a member of our product development team for PCB instrumentation in many design areas, including: 1. Precision measurement 2. Signal sourcing, and DSP
1天以前更新 兩週內0-5人應徵
2022-01-26

IC design Engineer

FULL_TIME
新竹市
104獵才顧問_一零四資訊科技股份有限公司
  • 大學以上
  • 四年以上工作經驗
  • 待遇面議
High speed IC design
三週以前更新 兩週內0-5人應徵
2022-01-03

RF IC Design Engineer

FULL_TIME
新竹縣竹北市
網聯通訊股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
Primary responsibility is to design and commerciallize broadband RF ICs for one of the following product lines : Wireless RF. You need proven record of RF/Mixed mode IC design in any one of the following fields: silicon tuner, wifi transceiver, Zigbee, UWB, or Bluetooth. Specific duties include : - Define broadband RF IC architecture and IC performance specifications - Design high performance and
3天以前更新 兩週內0-5人應徵
2022-01-24
華邦電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
【邀請您將104履歷同步上傳至華邦官方網站,將使您的履歷優先被主管看見】 1. DDR2/DDR3/DDR4/LPDDR2/LPDDR4 Circuit design 2. New Product engineering validation 3. FA analysis
一週以前更新 兩週內0-5人應徵
2022-01-20

Analog IC Design Engineer

FULL_TIME
新竹縣竹北市
安格科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
【工作內容】 1. 負責Serdes PHY Ex. DP/HDMI PHY的開發與維護工作。 2. 高速 PLL 與 RX Front End 的類比電路開發工作 3. Type-C / PD Controller的類比電路開發工作 【需求條件】 1. 碩士以上,電子電機、電機與控制、電信相關科系畢業。 2. 具三年以上USB、SATA、PCIE、HDMI、DisplayPort等PHY相關技術領域設計開發經驗者佳。 3. 碩士研究題目為PLL或 Serdes相關領域之應屆者可。
一週以前更新 兩週內0-5人應徵
2022-01-20
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Et
1天以前更新 兩週內0-5人應徵
2022-01-26
NVIDIA_英屬維京群島商輝達維京股份有限公司台灣分公司
  • 大學 碩士
  • 五年以上工作經驗
  • 待遇面議
We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized p
兩週以前更新 兩週內0-5人應徵
2022-01-12

Sr. Analog Design Engineer/Manager

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
-Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. -Experience in analog IP development that include ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies.
1天以前更新 兩週內0-5人應徵
2022-01-26

Sr. RF IC Design Engineer

FULL_TIME
新竹縣竹北市
網聯通訊股份有限公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
Primary responsibility is to design and commerciallize broadband RF ICs for one of the following product lines : Wireless RF. You need proven record of RF/Mixed mode IC design in any one of the following fields: silicon tuner, wifi transceiver, Zigbee, UWB, or Bluetooth. Specific duties include : - Define broadband RF IC architecture and IC performance specifications - Design high performance and
3天以前更新 兩週內0-5人應徵
2022-01-24
芯偉有限公司
  • 碩士
  • 五年以上工作經驗
  • 待遇面議
Job Descriptions: 1. Design and optimize transistor level circuits (analog/mixed-signal) for high-speed SerDes IP. 2. Behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems. 3. Supervise layout. 4. Silicon bring up, characterization, and debugging. 5. Design and silicon documentation. Requirements: 1. Very good fundamentals in analog/mixed-signal circuit design. 2.
兩個月以前更新 兩週內0-5人應徵
2021-10-31

Analog Design Engineer-High Speed(竹北)

FULL_TIME
新竹縣竹北市
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 一年以上工作經驗
  • 待遇面議
1. Analog circuit design and verification, such as OPAMP, Bandgap, ADC/DAC, PLL, and etc. 2. Power management circuit design and verification, such as LDOs, Charge Pumps, Switching Regulators, Gamma reference, and etc. 3. Whole chip integration with mixed-signal circuit. 4. HV I/O and ESD design.
一週以前更新 兩週內0-5人應徵
2022-01-20
翊傑科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
Description of Talent Job Requirement職務說明 1. 5+ years experiences in ASIC/SOC mixed-signal circuitry design is a plus 2. Experienced on any multiple design of following analog IPs: IO, band-gap, DLL, PLL, POR, Comparator/Amplifier, ADC,DAC analog circuit design, modification, testing/,validation. 3. Familiar with IO circuit design, Latch up/ESD protection mechanism , signal inte
2天以前更新 兩週內0-5人應徵
2022-01-25
台灣英飛朗股份有限公司
  • 碩士以上
  • 八年以上工作經驗
  • 年薪 1,500,000 ~ 3,000,000 元
Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of t
6天以前更新 兩週內0-5人應徵
2022-01-21

Senior RF IC Design Engineer (新竹)

FULL_TIME
新竹縣竹北市
立積電子股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
Design RF front end circuits including SAW/MEMS filter/PA/LNA/SW/Filter...etc. for vairious application systems
2天以前更新 兩週內0-5人應徵
2022-01-25
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