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CAD Engineer/Manager

FULL_TIME
新竹市
晶豪科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Tools automation script. 2. LVS and DRC rule maintenance. 3. Standard cell/ model/… Design & Layout library maintenance. 4. CAD tool evaluation, usage, maintenance & contact with EDA vendor. 5. EDA license maintain. 6. Provide training, documentation & user support. 7. 熟悉Synopsys, Cadence, mentor EDA 軟體.
一週以前更新 兩週內0-5人應徵
2021-05-05
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Foundry & In-house DRC/LVS/LPE/PERC rule deck maintain & creation 2. Physical verification CAD flow establishment & maintenance 3. Issue solving for ASIC project & IP development DRC/LVS problem
4天以前更新 兩週內0-5人應徵
2021-05-10

DFT CAD Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT design methodology development. (2) Flow development for MBIST, SCAN & ATPG. (3) In-house DFT design-kit/utility/script development.
一個月以前更新 兩週內0-5人應徵
2021-03-26

Physical IP CAD engineer

FULL_TIME
新竹縣竹北市
英屬維京群島商爍星有限公司台灣分公司
  • 碩士以上
  • 四年以上工作經驗
  • 月薪 80,000 ~ 200,000 元
1. EDA kits (DFT-MBIST/ATPG, Verilog, LEF, IR-model...) establishment, quality analysis and delivery for digital IPs (SRAM , Process detector) 2. Liberty (NLDM,CCS,LVF…) characterization, quality analysis and flow establishment for digital IPs (SRAM, Process detector) 3. Spice-netlist/GDS generation, Quality analysis and delivery for digital IPs (SRAM-compiler, Process detector) 4. Testing algorit
3天以前更新 兩週內0-5人應徵
2021-05-11

Analog CAD Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. IP design flow development 2. In-house utility development for IP design 3. EDA tool evaluation, usage, maintenance, Q&A window with tool vendor 4. 具備programming 能力 ( C/C++, TCL script, C-shell 或perl 其中一項以上 ) 5. Familiar with Virtuoso SKILL writing, Calibre rule writing, or other EDA tools is a plus. ※Requirements: 1. 熟 Verilog language, Verilog simulator 2. 有IP beh
4天以前更新 兩週內0-5人應徵
2021-05-10
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
4天以前更新 兩週內0-5人應徵
2021-05-10
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Front-end design flow development 2. Logic Synthesis, STA, LEC, ECO flow creation and consultant
4天以前更新 兩週內0-5人應徵
2021-05-10
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
Job description: a. Cell library and foundry process technology file management b. Technical support for standard cell and technology file related issues c. Circuit simulation and characterization d. Cell optimization for power and performance Nice to have: 1. Experience in cell library or circuit design 2. Advanced process (N16 and beyond) cell timing / power modeling experience is plus 3. Has
4天以前更新 兩週內0-5人應徵
2021-05-10
美商芯湖科技股份有限公司台灣分公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
Responsible for Front-End design flow (Synthesis, DFT insertion, LEC and STA) - compile RTL to gate netlist - insert DFT circuits (boundary scan, memory bist/bisr and scan chain) - run logic equivalence check - run static timing analysis Preferred requirement: 1. Master degree in EE or CS 2. Familiar with Front-End EDA tools (e.g. DesignCompiler, Tessent, Formality and PrimeTime)
三週以前更新 兩週內0-5人應徵
2021-04-22

Memory CAD Engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Implement memory compiler design utilities. 2. Develop memory IP design flow. 3. Familiar with C/C++, Tcl, and c shell. 4. Familiar with memory design, it’s plus 5. Familiar with liberty, verilog, tessent or DFT models, it’s plus
4天以前更新 兩週內0-5人應徵
2021-05-10
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
智原科技ASIC專案需要進行IP在設計流程上的各項驗證, 透過建構IP管理流程及自動化的工具來驗證, 確保IP設計的品質以順利使用於ASIC專案中。 過程中能夠學習IP完整驗證標準從設計流程考量,專案的實戰經驗累積及統計管理方法制定質量管控的流程步驟與驗證項目,從設計流程前段到佈局(layout)物理驗證流程,亦納入靜電防護及封裝相關規則檢查並藉由系統自動化的實現驗證流程SOP標準化。 職務說明: 1. Responsible for IP design data
4天以前更新 兩週內0-5人應徵
2021-05-10
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
兩個月以前更新 兩週內0-5人應徵
2021-01-27
佳易科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
A. Familiar with Standard Cell Circuit Design, verification of functionality, performance and power improvement methodology. B. Calculate cost( tools and man power ) of developing full set standard cell libraries C. Be able to judge and select required cells for target standard cell libraries D. Capable of defining timing specification for target standard cell libraries E. Plan and evaluate the R
一週以前更新 兩週內0-5人應徵
2021-05-05
台灣矽力杰科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
提供数字/混模电路设计的CAD 支持,负责公司内部数字IP 模块的开发和外部IP Vendor 的技术联络。 Digital CAD Engineer, working as part of the CAD team on development and support of digital and mixed signal design flows, driving the in-house development of digital IP building block, and acting as the primary technical liaison between the company and external IP vendors
兩週以前更新 兩週內0-5人應徵
2021-04-29
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1.Responsible for physical design flow development including APR, SI, IR, CTS, timing closure methodology development, flow automation 2. Project support/execution & collaboration with EDA vendors 3. APR flow/scripts/environment development for advanced process nodes ※Requirements: 1.Experience in APR, hierarchical design flow 2.Experience in physical design project execution 3.Fam
4天以前更新 兩週內0-5人應徵
2021-05-10
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