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SoC-Digital Design Engineer

FULL_TIME
新竹市
澳門商江左盟科技有限公司台灣分公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
(1) Familiar with DFT flow development(MBIST/SCAN/ATPG/BSCAN/LBIST). (2) Familiar with DFT realted flow and EDA tools(e.g. testmax/sms (3) Familiar with IC design flow(e.g. verilog/RTL/STA/LEC/Simulation (4) Familliar Unix Shell/Tcl/Perl & programming skills. (5) Million-gate SOC design experience is a plus.
三週以前更新 兩週內0-5人應徵
2021-09-27
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, fun
一週以前更新 兩週內0-5人應徵
2021-10-12
Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
Job Description: The selected candidate will be a key member of the Synopsys DesignWare Processor team in Hsinchu and involved in the development of leading edge DesignWare processor IP products such as NN accelerators, vision processors, as well as high-performance or energy-efficient general purpose processors. The responsibility could vary from architecture analysis, micro-architecture, logic d
一週以前更新 兩週內6-10人應徵
2021-10-12
智成電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.In charge of digital circuit design/verify by Verilog/VHDL 2.Familiar with ASIC design flow or FPGA development is a plus. 3.Familiar with MCU SoC design is a plus. 4.Familiar with RF baseband design is a plus.
2天以前更新 兩週內0-5人應徵
2021-10-18

Digital IC Design Engineer

FULL_TIME
新竹縣竹北市
台灣瑞阩科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
Digital IC design, verification and physical implementation. Synthesis, STA, timing closure. FPGA integration. [ Digital IC Desing Engineer - I ] Experience in audio/voice signal processing (Filter, EQ, DRC.. ) is preferred. Digital IP design and verification. [ Digital IC Desing Engineer - II ] SoC integration(floorplan design, package bonding) and verification Power domain design.
1天以前更新 兩週內0-5人應徵
2021-10-19

ASIC Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for digital designer with solid digital design and technical skills. The responsibility is to deliver Sub-System level design and corresponding verification environment for high performance System-on-Chip. 2.Responsible for RTL, integration and verification of IP and customer specific digital design content. Expect to contribute to methodology development and effic
一週以前更新 兩週內0-5人應徵
2021-10-12

Standard cell design engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
5天以前更新 兩週內0-5人應徵
2021-10-15

Digital IP Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
※Requirements: 1. DDR/LPDDR/GDDR/HBM logic design and verification 2. RTL design 3. Digital Design Checks : CDC, LEC, STA, and etc. ※其他條件 1. Over 3-year digital design experiences 2. Familiar with DDR/LPDDR/HBM/SerDes or DSP is plus 3. Familar with digital IC front-end design flow such as Verilog RTL design, Synopsys Design Compiler, LEC, Spygalss, PrimeTime STA
一週以前更新 兩週內0-5人應徵
2021-10-12
美商超微半導體股份有限公司台灣分公司
  • 大學以上
  • 六年以上工作經驗
  • 待遇面議
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand col
2小時以前更新 兩週內0-5人應徵
2021-10-20
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
Micron is seeking an ASIC Development - Chip Lead for Micron’s ASIC project. In this role, you will be responsible for leading development of SOC design in our storage-based controllers from Specification to transfer to volume production. You should have strong knowledge and proven hands-on experience with many aspects of the SOC design and implementation flow – including coverage driven verificat
一個月以前更新 兩週內0-5人應徵
2021-09-17
智原科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1. One of the Key Serdes protocol (PCIe, SATA, USB, VBO, MIPI etc.) 2. Knowledge and design experience of PCS 3. Knowledge and design experience of digital flows & FPGA validations 4. Hands-on experience on post-silicon debug 5. Capable to communication in English
三週以前更新 兩週內0-5人應徵
2021-09-29

Digital IC Design Engineer (Hsinchu)

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Digital IC design, or verification, or FPGA, or STA timing closure. Algorithm, DSP, Communication. SOC development flow, from architect, Specification, design, verification, timing closure, tape out, mass-production. Verilog and/or writing shell/tcl scripts. 2. Good sense of debug, meaning, identify the root cause, resolve the problem. Working with Design, Verification, FW teams. Po
兩週以前更新 兩週內0-5人應徵
2021-10-05

APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 3.Requirement: 3-1. Familiar with ASIC design flow相關尤佳 3-2. Hands on APR physical design from netlist to DRC/LVS tapeout experience is required 3-3. Familiar with hierarchical and/or low power design flow相關尤佳
5天以前更新 兩週內11-30人應徵
2021-10-15

SoC Design Engineer

FULL_TIME
新竹市
華晶科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1. High speed interface IP ( MIPI, USB, PCI-e) design, integration and verification 2. DDR IP design, integration and verification 3. Embedded CPU ( ARC, RISC-V, ARM) based on chip bus peripheral design, integration and verification 4. RTL to FPGA porting and verification 5. Hardware emulator porting and verification
6天以前更新 兩週內0-5人應徵
2021-10-14
台灣超捷國際股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
Job Description: In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless SoC Development. Your scope of work includes but not limited to: • Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan. • Work closely with front-end te
三週以前更新 兩週內0-5人應徵
2021-09-28
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