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2195 筆查詢結果

Analog IC design engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://tinyurl.com/y3ctj87q 【Description】 1. Design analog KPI circuitry of high speed ADC, sensor and regulator etc. 2. Design analog test vehicle to create ADLG (analog design/layout guideline) 3. Enable cross functions and customers to extract and characterize device parameters 【Qualifications】 1. MS
兩個月以前更新 兩週內0-5人應徵
2021-03-15

FPGA Design Engineer

FULL_TIME
新竹縣竹北市
美商艾科斯羅國際股份有限公司台灣分公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
Seeking a design engineer with 3 to 8 years of experience. Reporting to the Manager of HW Engineering ASIC & FPGA you will provide innovative solutions to our FPGA design effort. This is a unique opportunity to create first to market chip designs and to contribute to the future of ATE instruments within COHU Semiconductor Test Group products. Essential Duties and Responsibilities: This role pr
2天以前更新 兩週內0-5人應徵
2021-07-23

Physical Design Engineer

FULL_TIME
新竹市
益芯科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Must have BS in EE/CE/CS of relevant experience in IC design field. 2. Familiar with IC design flow : *Chip integration and floorplan *APR physical design *Fully customized layout *DRC/LVS to tapeout 3. Engineering discipline, passion, and willing to teamwork. 4. Circuit knowledge and analog/logic design relevant experience would be a plus.
6天以前更新 兩週內0-5人應徵
2021-07-19

Soc IC Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1.Lead a team to complete the front-end design tasks from RTL design to netlist. 2.Main job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. 3.Support other functional teams (such as IP team, DFT team, and P&R team) to deliver an SoC/ASIC. 4.Use communication and leadership skills to help the team to achieve the goal. ※R
6天以前更新 兩週內0-5人應徵
2021-07-19

Circuit Design Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 博士
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://tinyurl.com/v7k3d7d 【Description】 1.Circuit Design for memory related testchips 2.Research on circuit designs for high-density memory and computing-in-memory 3.Conduct research in the field of circuit designs for future high-density memory and computing-in-memory for AI applications in collaboration
兩個月以前更新 兩週內0-5人應徵
2021-03-15
Cypress Semiconductor_新加坡商賽普拉斯半導體股份有限公司台灣分公司
  • 大學以上
  • 八年以上工作經驗
  • 待遇面議
The IC design team of Infineon ICW is looking for a hands-on, team-oriented and self-motivated digital design engineer. In this role, the engineer will be responsible for IoT Bluetooth IP development. We have world's top intelligent IC design teams include system, digital/analog design, firmware, software teams all over the world. You will have the chance to work with and be part of them. Detai
3天以前更新 兩週內0-5人應徵
2021-07-22

Sr. Circuit Design Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://tinyurl.com/ydcad742 【Description】 - Design full custom read and write circuits at transistors level - Simulate and analyze the circuit design using transistor level simulators. - Extract the layout and perform post-layout simulations and verification - Floorplan physical implementation and leafcell
兩個月以前更新 兩週內0-5人應徵
2021-03-15

Analog IC Design Engineer

FULL_TIME
新竹縣竹北市
台灣瑞阩科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
Familiar with one of analog circuits design as below: 1. Sigma-delta ADC/DAC design for audio application 2. PLL design 3. Bandgap voltage reference 4. POR 5. LDO 6. Charge pump 7. Oscillator 8. Voltage detector 9. Headphone power amplifier Provide Analog IP MP solution in CP/FT. Enjoys working side by side with partners, colleagues and teams on tough problems.
3天以前更新 兩週內0-5人應徵
2021-07-22
Cypress Semiconductor_新加坡商賽普拉斯半導體股份有限公司台灣分公司
  • 大學以上
  • 八年以上工作經驗
  • 待遇面議
Sr.staff (2) Job Title: Design Design Engineer (2) Number of Positions: 1 Job Location: Hsinchu Degree: MS Hiring Manager: Wen-Hsin Huang Job Description: The IC design team of Infineon ICW is looking for a hands-on, team-oriented and self-motivated digital design engineer. In this role, the engineer will be responsible for IoT platform development. We have world's top intelligent IC design te
3天以前更新 兩週內0-5人應徵
2021-07-22

Analog IC Design Engineer

FULL_TIME
新竹市
衡宇科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Analog/mixed-signal IC design
6天以前更新 兩週內0-5人應徵
2021-07-19

analog ic design engineer

FULL_TIME
新竹縣竹北市
芯偉有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
familiar with one of analog circuits design as below: 1. phase locked loop design 2. sar ADC design 3. delta-sigma ADC design 4. clock data recovery circuits design
一個月以前更新 兩週內0-5人應徵
2021-05-31
智成電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.In charge of digital circuit design/verify by Verilog/VHDL 2.Familiar with ASIC design flow or FPGA development is a plus. 3.Familiar with MCU SoC design is a plus. 4.Familiar with RF baseband design is a plus.
2天以前更新 兩週內0-5人應徵
2021-07-23

Analog IC Design Engineer

FULL_TIME
新竹縣竹北市
安格科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
1. High-speed I/O design, including the design of SERDES for rate 5G or higher.
6天以前更新 兩週內0-5人應徵
2021-07-19
創意電子股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
Job Descriptions: 1.Lead a subsystem front-end design/verification tasks from RTL to netlist. 2.Subsystem includes AMBA based subsystem or high speed communication subsystem like PCIe. 3.Main job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. Hands-on capability is necessary 4.Use communication and leadership skills to help the team t
6天以前更新 兩週內0-5人應徵
2021-07-19

DDR/HBM PHY Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. HBM / DDR IO circuit design, layout reviewing and PI/SI simulation 2. HBM / DDR PHY design, implementation and verification 3. Needs co-work with controller designer 4. Needs prepare verilog model/lef/lib/db/gds/spi to customer 5. Needs prepare PR guide and discussion with APR engineer ※Skill: 1. Familiar with Prime Time 2. Had experience with backend flow.(At least once tape o
6天以前更新 兩週內0-5人應徵
2021-07-19
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