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2612 筆查詢結果

Circuit Design Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 博士
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://tinyurl.com/v7k3d7d 【Description】 1.Circuit Design for memory related testchips 2.Research on circuit designs for high-density memory and computing-in-memory 3.Conduct research in the field of circuit designs for future high-density memory and computing-in-memory for AI applications in collaboration
兩個月以前更新 兩週內0-5人應徵
2021-03-15

Sr. Circuit Design Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://tinyurl.com/ydcad742 【Description】 - Design full custom read and write circuits at transistors level - Simulate and analyze the circuit design using transistor level simulators. - Extract the layout and perform post-layout simulations and verification - Floorplan physical implementation and leafcell
兩個月以前更新 兩週內0-5人應徵
2021-03-15
美商超微半導體股份有限公司台灣分公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand col
6天以前更新 兩週內0-5人應徵
2021-06-16
新必優資訊股份有限公司
  • 學歷不拘
  • 一年以上工作經驗
  • 待遇面議
- Block level and sub-block floor-planning - Discuss SRAM placement with PD team during block level floor-planning stage - Placement optimization for timing and resolve congestion - Clock tree synthesis and clock tree optimization for timing - Routing and routing optimization for post-route timing and resolving congestion - Clean-up DRC error - Post-route timing ECO - Metal ECO - Clean post-route
一週以前更新 兩週內0-5人應徵
2021-06-15
印度商威普羅股份有限公司台灣分公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
· Block level and sub-block floor-planning · Discuss SRAM placement during block level floor-planning stage · Placement optimization for timing and resolve congestion · Clock tree synthesis and clock tree optimization for timing · Routing and routing optimization for post-route timing and resolving congestion · Clean-up DRC error · Post-route timing ECO · Metal ECO · Clean post-route t
一小時以內更新 兩週內0-5人應徵
2021-06-22

Analog Design Engineer(SVT)

FULL_TIME
新竹市
聯詠科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
【產品線描述 】 CMOS image sensor for consumer, industrial and automotive applications. 【工作說明 】 1.Analog and mixed-signal circuit design for image sensors, responsibilities will include, but are not limited to, the following: 1-1. Design of analog/mixed-signal circuits including one of the following catalogs: (1) charge pump, LDO regulator, bandgap, Op Amp; (2) high-speed SRAM or MIPI;
5天以前更新 兩週內0-5人應徵
2021-06-17
世界先進積體電路股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1.Responsible for SRAM Macro / SRAM Compiler Design. 2.SRAM Circuit Development; Verification and Maintenance
一個月以前更新 兩週內6-10人應徵
2021-05-11
智成電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.In charge of digital circuit design/verify by Verilog/VHDL 2.Familiar with ASIC design flow or FPGA development is a plus. 3.Familiar with MCU SoC design is a plus. 4.Familiar with RF baseband design is a plus.
三週以前更新 兩週內0-5人應徵
2021-05-28

Sr. Design Engineer

FULL_TIME
新竹縣竹北市
萬有半導體有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
Circuit Designer- Do circuit design tasks for new product development, and work closely with AE, Layout Engineer and TE.
4天以前更新 兩週內0-5人應徵
2021-06-18
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
5天以前更新 兩週內0-5人應徵
2021-06-17
安霸股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
At Ambarella, we gather brilliant minds together to push computer vision technology forward. We're seeking a VLSI design verification (DV) engineer who will verify our most cutting-edge SOCs and components inside SOC. A DV engineer works with designers to make sure design meets specification. Firstly, a DV engineer creates a test plan. A test plan plots in details on what tests you need/want
一小時以內更新 兩週內0-5人應徵
2021-06-22

Senior FPGA Design Engineer

FULL_TIME
新竹市
美商邁凌科技有限公司台灣分公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
MaxLinear is seeking a Senior FPGA Design Engineer to join our growing team. You will be responsible to execute FPGA IP projects and deliver our IP to customers. This role is hands-on and encompasses architecture to implementation, including verification, testing and documentation. In this role, you will focus on the following: • Design and develop FPGA and ASIC IP used in customer wireless produ
一週以前更新 兩週內0-5人應徵
2021-06-15
美商邁凌科技有限公司台灣分公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
MaxLinear is seeking a Principal ASIC Design Engineer to lead and execute projects, define customer-specific product definition, and deliver our IP. This role is hands-on and encompasses architecture to implementation, including verification, testing and documentation. In this role, you will: • Work with customers and customize product definition specific to their system-on-chip • Work with algor
5天以前更新 兩週內0-5人應徵
2021-06-17

Principle Design Engineer

FULL_TIME
新竹市
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 七年以上工作經驗
  • 待遇面議
Micron’s vision is to transform how the world uses information to enrich life for all. ​ Join an inclusive team focused on one thing: using our expertise in the relentless pursuit of innovation for customers and partners. The solutions we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainabi
一個月以前更新 兩週內0-5人應徵
2021-05-11
晨曦智聯有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
符合以下其中之一項: 1. Pipeline ADC or SAR ADC Design 2. Delta-Sigma ADC or DAC 3. DAC Design 2. Analog filter Design 3. Bandgap, LDO, Oscillator Design
兩週以前更新 兩週內0-5人應徵
2021-06-02
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