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創意電子股份有限公司
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1. 工作地點:Hsinchu 2. Responsible for ASIC tech activities of pre-sale projects, including tech capability promotion, Effective communication with clients for tech and business needs, tech proposal delivery and SOW drafting. 3. Handle ASIC program management and key issue resolving from Netlist-in to Mass production. 4. Business travel is expected. ※Requirements: 1. 10~15 year
3天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
DFT Design Engineer - MBIST / SCAN ※Job Contents: 1. 工作地點:台北/新竹/台南. 2. Implement of MBIST / SCAN 3. Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check 4. Discuss with Test Engineers to provide solutions to DFT testing ※Requirements: 1. Graduated in EE or related Engineering 2. Proficient in programming skill and UNIX shell. 3. Familiar with Verilog / RTL
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Design and optimize transistor level circuits (analog/mixed-signal) for high-speed SerDes IP. 2. Behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems. 3. Supervise layout. 4. Silicon bring up, characterization, and debugging. 5. Design and silicon documentation. 6. Work with cross functional teams to bring IP from schematics to mass productio
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1. Work with GUC's customers to define a competitive packaging solution. 2. Package design, solve technical challenge, and all package related actions follow up. 3. Work with GUC signal integrity engineer, substrate designer and thermal designer to come up with a cost effective package. 4. New package technology design flow development ※Requirements: 1.機械/電子/電機工程/材料工程相
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took respoinsibility of planing low-power structure and review flow(CPF/UPF) 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar wi
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 1.Develop power and IR verification methodology to ensure chip power integrity. 2.Perform IR verification, including power calculation, IR drop and EM analysis, and library power modeling. 3.Develop design flow to analyze the quality of power delivery network, including power grid, bump assignment, and chip-package co-design. 4.Support power network improvement. Job Requirements
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
Job description: a. Cell library and foundry process technology file management b. Technical support for standard cell and technology file related issues c. Circuit simulation and characterization d. Cell optimization for power and performance Nice to have: 1. Experience in cell library or circuit design 2. Advanced process (N16 and beyond) cell timing / power modeling experience is plus 3. Has
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 ※Job Contents: 1.Location:新竹/台北/台南 2. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 3. Support STA timing analysis and fixing 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence EDI or Synopsys ICC. 2. TOEIC 730~855 is prefer
3天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
GUC Mixed Signal Department ●符合以下經驗之一 1. PLL/DLL/VCO circuit desgin 2. ADC circuit design 3. DAC circuit design 4. High Speed SerDes circuit design 5. 熟Matlab佳 6. 熟mixed signal design flow佳(ex. Inductor extraction, RC extraction, mixed mode simulation) 自我推薦獎金辦法: 1.期間限定:即日起至2021/09/30止 2.適用職缺: 職缺上有註明”享自我推薦獎金,獎金最高15萬”者適用 3.獎勵內容: 相關年資1
3天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. New product introduction 2. Production yield and quality improvement ※Requirements: 1. In semiconductor filed >= 3years 2. Advanced technology process integration experience, with Product or Device engineering is plus 3. With basic wafer test concept 自我推薦獎金辦法: 1.期間限定:即日起至2021/09/30止 2.適用職缺: 職缺上有註明”享自我推薦獎金,獎金最高15萬”者適用 3.獎勵內容: 相關
3天以前更新 兩週內大於30人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Work with GUC's customers to define a competitive packaging solution. 2. Package design and the related actions follow up. 3. Work with GUC signal integrity engineer, substrate designer and thermal designer to come up with a cost effective package ※Requirements: 1.機械/電子/電機工程相關研究所(含)以上畢 2.熟悉Cadence Allegro Package Designer, Autocad 3.熟悉各種類型之封裝及基
3天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
※Job Contents: 1. Analog/Mixed-signal IC verification (ex: High-speed AFE, PLL, Serdes etc...) 2. Define test plans, develop automated tools, verify, test, debug and make silicon report. ※Requirements: 1. Develop automated programs (ex: Python, LabVIEW…) 2. Familiar with test equipment, such as: oscilloscope, spectrum analyzer, signal generator, LA, power supply, etc. 3. Analog/mixed signal/hig
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1. In charge of substrate design with variable package type (F/C and W/B package). 2. Co-work with package designer/ electrical engineer to optimize the pad/bump location and substrate design. ※Requirements: 1. 專科以上,電子電機/機械工程相關科系畢。 2. 工作經驗:1年以上。 3. Familiar with Cadence APD. 4. Good working attitude (Positive, Proactive, Careful and Responsible). ※加分
3天以前更新 兩週內6-10人應徵
2021-07-26
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. Package/PCB Model extraction by EM tooling. 2. Whole system level signal/power integrity modeling, characterization and simulations including PCB, package and chip IOs. 3. Silicon chip results correlation with simulation 4. Co-simulation flow development 5. Co-work with IC designer to define specification and solve the silicon related signal and power integrity problems in the s
3天以前更新 兩週內0-5人應徵
2021-07-26
創意電子股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱 Physical Design Technical Manager (APR) ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2, Innovus w
3天以前更新 兩週內6-10人應徵
2021-07-26
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