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Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
This position will join the ARC Processor group at Synopsys and will be part of the Functional Safety R&D Team. As a member of the ARC Functional Safety Team you will gain understanding of the leading vision and neural network processors and contribute to architecting and designing state of the art safety features and mechanisms for ARC processor cores. You will leverage your design skills and f
一週以前更新 兩週內0-5人應徵
2021-11-19
Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
Responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including compilers, routers, utilities, databases, etc. Determines hardware compatibility and/or influences hardware design. Usually developing professional expertise, and may apply company policies and procedures to resolve a variety of issues. At a minimum, has working knowledge of
一週以前更新 兩週內11-30人應徵
2021-11-15
智成電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.In charge of digital circuit design/verify by Verilog/VHDL 2.Familiar with ASIC design flow or FPGA development is a plus. 3.Familiar with MCU SoC design is a plus. 4.Familiar with RF baseband design is a plus.
一個月以前更新 兩週內0-5人應徵
2021-10-18
科締納科技股份有限公司_Cortina Systems Taiwan Limited
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
Senior level ASIC design engineer [Responsibility] Module level design and verification activities including: • Design digital control or datapath logic using Verilog HDL • Design synthesis using RTL Complier • RTL linting using preferred lint tool SoC integration FPGA design and lab debug
兩個月以前更新 兩週內0-5人應徵
2021-09-27

ASIC Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for digital designer with solid digital design and technical skills. The responsibility is to deliver Sub-System level design and corresponding verification environment for high performance System-on-Chip. 2.Responsible for RTL, integration and verification of IP and customer specific digital design content. Expect to contribute to methodology development and effic
6天以前更新 兩週內0-5人應徵
2021-11-22

Standard cell design engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
一週以前更新 兩週內6-10人應徵
2021-11-15

SoC/ASIC/IP digital design engineer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
- Design/development of SoC subsystem blocks. - Responsible for SOC system Integration/Verification - Generate detailed micro-architecture technical specifications and systems requirements and deliver the design - Work closely with verification team to develop verification plans and actively participate in debug phase - Work hands-on and own their design through the full SoC/ASIC development p
6天以前更新 兩週內0-5人應徵
2021-11-22

Senior Digital Design Engineer( Zhubei)

FULL_TIME
新竹縣竹北市
Dialog Semiconductor_德商戴樂格半導體有限公司台灣分公司
  • 學歷不拘
  • 工作經驗不拘
  • 待遇面議
Working as a Senior Digital Design Engineer based in Zhubei, you will: • Design optimized digital blocks meeting functional, cost, and low power constraints and ensure spec compliance. • Cover digital backend design from synthesis, static timing, and logic equivalent checking. • Interface with P&R for digital hand-off and post layout verification. • Collaboration with analog engineers and test eng
3天以前更新 兩週內0-5人應徵
2021-11-25
毅誠電子有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
工作項目: 數位IC/IP 設計開發與維護,FPGA驗證 應徵條件: 1. 碩士以上; 電機工程、電子工程等相關科系畢業為主。 2. 熟悉digital circuit design。 3, 具Verilog 相關經驗、熟悉FPGA/ASIC發展流程。 4, 具 peripheral bus (SPI, SMBUS, UART) 經驗者佳 5, 熟悉 AMBA protocol. 6. 熟悉 高速介面(SATA, PCIE) 規格 或相關經驗者佳 7. 具有數位IC設計 工作經歷 2年以上
4天以前更新 兩週內0-5人應徵
2021-11-24
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
Digital circuit design for DTCO(Design technology Co-Optimization)
4天以前更新 兩週內0-5人應徵
2021-11-24

ASIC DV Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for DV engineer with solid digital verification technical skills. The responsibility is to deliver high-performance SOC with the highest standard of quality for world-wide customer in the process of 16nm or under. 2.This position will be responsible for working with Design Engineers in verification and validation of SOC. Participate in design reviews and recommend
6天以前更新 兩週內0-5人應徵
2021-11-22

Digital IP Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
※Requirements: 1. DDR/LPDDR/GDDR/HBM logic design and verification 2. RTL design 3. Digital Design Checks : CDC, LEC, STA, and etc. ※其他條件 1. Over 3-year digital design experiences 2. Familiar with DDR/LPDDR/HBM/SerDes or DSP is plus 3. Familar with digital IC front-end design flow such as Verilog RTL design, Synopsys Design Compiler, LEC, Spygalss, PrimeTime STA
6天以前更新 兩週內0-5人應徵
2021-11-22

ASIC/ECC DESIGN Engineer (Hsinchu)

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
• You will be involved in developing storage chipsets. • The work requires participation in defining functional specifications with the ASIC architect and developing the design in Verilog. • Support verification, circuit, and test groups throughout the design cycle and silicon bring up. • Work with multi-disciplinary groups to ensure designs are delivered on time and with the highest quality
2天以前更新 兩週內0-5人應徵
2021-11-26

Sr. ASIC Design Engineer(竹北)

FULL_TIME
新竹縣竹北市
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 大學 碩士
  • 五年以上工作經驗
  • 待遇面議
1. Demonstrate an expert knowledge of System Verilog (SV) or similar verification language 2. Demonstrate an expert knowledge of Verilog for chip design and verification 3. Must be able to read specifications, create a MAS, then implement the design 4. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and
6天以前更新 兩週內0-5人應徵
2021-11-22
Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
The ideal candidate will be a member of a next generation advanced NVM design team and have the opportunities to participate in IP generation. A team player with good written and verbal communication skills, and is self-motivated, detail oriented, and able to work with cross-functional teams. ASIC Design Engineer Introduction: https://www.youtube.com/watch?v=co3BC-BUTLg Responsibilities and Duti
三週以前更新 兩週內6-10人應徵
2021-11-04
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