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3067 筆查詢結果

Standard cell design engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
6天以前更新 兩週內0-5人應徵
2021-10-22

DV Methodology Engineer

FULL_TIME
新竹市
聯發科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
由於 先進製程 與 高整合度晶片 需要 較長的研發時間 及 高製造成本, DV (Design Verification) 已成為 聯發科技 晶片開發流程中 不可或缺的一環 . CDG DV部門負責 開發與執行 最高整合度 Smartphone, TV 與 ASIC 驗證工程. 內容包含: 整合型驗證環境開發, 大數據分析與效能改善, BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行. 工作中需要 設計 及 精進 Verification plan/methodology/be
2天以前更新 兩週內0-5人應徵
2021-10-26
瑞昱半導體股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
Job function: 1. Work with digital design team for High performance/congestion core synthesis. 2. Responsible for front-end design implementation methodology research and development. 3. projects coordination and management. Requirement: 1. MS with 5+ years of experience in Front-end Methodology Design. 2. Familiar with Linux environment and tcl/perl scripts. 3. Familiar with ASIC design flow. 4.
1天以前更新 兩週內0-5人應徵
2021-10-27
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
- Co-work w/ foundry/EDA vendors to define best PD imp recipes - Explore EDA tool new features and introduce to project team - Define proper FOM to project DTCO opportunities - Optimize PG structure for best resource and IR/EM concerns, including pillar types, via stacking layers - Help project team revise scripts, provide guidelines/checkers to check PD quality and feedback potential issues - Bui
2天以前更新 兩週內6-10人應徵
2021-10-26
NVIDIA_英屬維京群島商輝達維京股份有限公司台灣分公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to sol
1天以前更新 兩週內0-5人應徵
2021-10-27
安霸股份有限公司
  • 碩士以上
  • 七年以上工作經驗
  • 待遇面議
1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. 3.Implement and enhance design infrastructure for the increases on productivity and quality.
6天以前更新 兩週內0-5人應徵
2021-10-22

APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 3.Requirement: 3-1. Familiar with ASIC design flow相關尤佳 3-2. Hands on APR physical design from netlist to DRC/LVS tapeout experience is required 3-3. Familiar with hierarchical and/or low power design flow相關尤佳
6天以前更新 兩週內11-30人應徵
2021-10-22

ICD-IC Design Engineer

FULL_TIME
新竹市
點序科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. Team player 2. Familiarity with SoC design methodology 3. USB, Flash memory card and SSD experience is a plus 4. Support business travel
2天以前更新 兩週內0-5人應徵
2021-10-26

Senior Digital Design Engineer( Zhubei)

FULL_TIME
新竹縣竹北市
Dialog Semiconductor_德商戴樂格半導體有限公司台灣分公司
  • 學歷不拘
  • 工作經驗不拘
  • 待遇面議
Working as a Senior Digital Design Engineer based in Zhubei, you will: • Design optimized digital blocks meeting functional, cost, and low power constraints and ensure spec compliance. • Cover digital backend design from synthesis, static timing, and logic equivalent checking. • Interface with P&R for digital hand-off and post layout verification. • Collaboration with analog engineers and test eng
1天以前更新 兩週內0-5人應徵
2021-10-27
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
As a Design Verification Engineer within the ASIC CXL Development at Micron, you will be responsible for defining efficient and coverage-driven testbench for high-quality design delivery. Job Responsibilities: Verification plan definition, DV environment development in SV/UVM and SV/C Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level. Suppor
兩個月以前更新 兩週內0-5人應徵
2021-07-14

System Design Engineer

FULL_TIME
新竹市
聯發科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
As a system design engineer in the Computing and AI team, you will develop advanced technologies for power and thermal early estimation. Since power and thermal are major constraints for increasing mobile computing system performance, this role will be involved performance-power-thermal (PPT) optimization for mobile computing system in the pre-silicon design stage. Job Description: 1. Develop sys
2天以前更新 兩週內0-5人應徵
2021-10-26

資深APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Physical design of multi-million instance-count SOC project. Physical design activities include floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. (APR Support) 2.Build advanced physical design methodology to facilitate UDSM design project for timing/power/DFM closure and CPU/GPU hardening. 3.Requirement: 3-1. Familiar with Cadence EDI Platform and/or Syno
6天以前更新 兩週內0-5人應徵
2021-10-22
台灣超捷國際股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
Job Description: In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless SoC Development. Your scope of work includes but not limited to: • Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan. • Work closely with front-end te
一週以前更新 兩週內0-5人應徵
2021-10-20
Qualcomm Semiconductor Corporation_高通半導體有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
The IC Package System Design Team at Qualcomm has an opening for Package/System Design Engineer. This team is responsible for road mapping, architecting, design methodology, design implementation and verification for all Qualcomm package products (Digital, RF, Analog, PMIC, etc...). Job responsibilities for this position include package selection, package design, and package EE modeling. This invo
一週以前更新 兩週內6-10人應徵
2021-10-21

Design Verification Engineer

FULL_TIME
新竹縣竹北市
耐能智慧股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to delive
2天以前更新 兩週內0-5人應徵
2021-10-26
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