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佳易科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Gb Ethernet Controller IP Development on 0.13um Technology 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library
一週以前更新 兩週內0-5人應徵
2021-11-22
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Et
一週以前更新 兩週內0-5人應徵
2021-11-22
智原科技股份有限公司
  • 碩士以上
  • 七年以上工作經驗
  • 待遇面議
熟悉Giga-bits Ethernet PHY analog design, system operation, Voltage-mode driver, Receiver analog front-end
兩週以前更新 兩週內0-5人應徵
2021-11-15

Sr. Analog Design Engineer/Manager

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
-Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. -Experience in analog IP development that include ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies.
一週以前更新 兩週內0-5人應徵
2021-11-22
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Engage customer and IP promotion. 2. IP issue tracking and technical support. ※Requirements(either one of below items) 1. IP design/integration Experience. 2. Familiar with either one of the below protocols:PCIe/Ethernet/SATA/HBM/DDR and knowledge of system debugging. 3. Rich experiences to deal engagement and customer support.
一週以前更新 兩週內0-5人應徵
2021-11-22
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, fun
一週以前更新 兩週內0-5人應徵
2021-11-22

CPU IP Design Engineer

FULL_TIME
新竹市
安興技術諮詢股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
Job Description For this role we are looking for engineers who are capable of owning one or more functional blocks for CPU IP related products with quality of delivery through all phases of related engineering processes. This includes: • Participating in engineering feasibility analysis, review, and determination for requirements of market, product, architecture, and engineering process; • D
一個月以前更新 兩週內0-5人應徵
2021-10-25

High Speed IP Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
- High Speed Interface IP and Subsystem Design - IP configuration and IP level verification - Subsystem Design including Link, PHY and Sub-controller - Subsystem Verification and Bring-up - Subsystem Level Sanity Check : Lint, CDC, Synthesis - Subsystem level SDC generation and verification (PT constraint) - Subsystem level UPF generation and verification (VC LP) - Performance Profiling, and Power
3天以前更新 兩週內0-5人應徵
2021-11-26

Sr. Principal RF Design Engineer

FULL_TIME
新竹縣竹北市
香港商安森美半導體有限公司台灣分公司(ON Semiconductor)
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
• Responsible for specify, design and productize RF transceivers for WIFI chipsets. • Involved in early stages for the design concept, working close with other teams to narrow down optimum specification and best system performance. • Design with various sub micron technology nodes. • Leadership for block design, macro design and top level integration.
一週以前更新 兩週內0-5人應徵
2021-11-17
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
1. 10+ years experience with MS in EE or CS 2. Hands on silicon design and bring up experiences 3. Experiences with data communication protocols such as PCI Express, SuperSpeed USB, SATA, etc. 4. Experiences in mixed signal design with good understanding of analog circuit design 5. Design experience with PCIe 3.0 and 4.0 is a plus
一週以前更新 兩週內0-5人應徵
2021-11-22
佳易科技股份有限公司
  • 碩士以上
  • 六年以上工作經驗
  • 待遇面議
1.0.13um & 0.18um ASIC Memory cell and Memory Compiler Development 2.Library characterization and validation: Generate and validate library model, i.e. .lib, .lef, .v, etc. 3.Library usage guideline and sign-off criteria a)Provide synthesis and optimization strategy for custom library b)Simulate and define sign-off criteria for custom library
一週以前更新 兩週內0-5人應徵
2021-11-22

DDR Phy Designer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Analog circuit design (Bandgap, Regulator, DLL) 2. High speed IO circuit design (DDR3/DDR4/LPDDR3/LPDDR2) 3. DDR PHY structure design (DDR3/DDR4/LPDDR3/LPDDR2)
兩週以前更新 兩週內0-5人應徵
2021-11-15
智原科技股份有限公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
Ethernet PHY 的演算法開發: 具備熟悉數位通訊, 數位訊號處理, Digital Filter, Equalizer, Timing Recovery, Auto-Gain control, Baseline wander correction & echo cancellation
兩週以前更新 兩週內0-5人應徵
2021-11-15

Sr. Digital IC Design Engineer_2101605

FULL_TIME
新竹縣竹北市
Marvell_邁威爾科技有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
The Opportunity Marvell connects the connected car with high-quality AEC‐Q100 qualified products and solutions that include storage, bridges, and Ethernet domains providing automotive infotainment, wired/ wireless connectivity, and coapplication processor platforms that function in the Automotive Ethernet and Automotive Storage. Job Responsibilities: The candidate will involve in the next genera
一週以前更新 兩週內0-5人應徵
2021-11-18
Cypress Semiconductor_新加坡商賽普拉斯半導體股份有限公司台灣分公司
  • 大學以上
  • 八年以上工作經驗
  • 待遇面議
Sr.staff (2) Job Title: Design Design Engineer (2) Number of Positions: 1 Job Location: Hsinchu Degree: MS Hiring Manager: Wen-Hsin Huang Job Description: The IC design team of Infineon ICW is looking for a hands-on, team-oriented and self-motivated digital design engineer. In this role, the engineer will be responsible for IoT platform development. We have world's top intelligent IC design te
3天以前更新 兩週內0-5人應徵
2021-11-26
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