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CAD Engineer

FULL_TIME
新竹市
智成電子股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1. Front-end IC design flow development/maintain/support 2. Standard cell library design & modeling & maintain 3. IC tape out project support
2天以前更新 兩週內0-5人應徵
2021-10-18

Standard cell CAD engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,主要負責Standard cell應用端效能最佳化分析。 1.Pre-layout/Post-layout PPA analysis 2.Standard cell design and layout optimization 3.Technical support of in-house & 3rd-party libraries。 4.需求條件: 4-1. 熟悉 physical design flow 4-2. 具備physical design PPA and routability 分析經驗尤佳 4-3. 具備high speed synthesis, DFT, or STA sign-off經驗尤佳 4-4.
5天以前更新 兩週內0-5人應徵
2021-10-15

CAD Engineer

FULL_TIME
新竹市
瓦雷科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.
8小時以前更新 兩週內0-5人應徵
2021-10-20

CAD Engineer/Manager

FULL_TIME
新竹市
晶豪科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Tools automation script. 2. LVS and DRC rule maintenance. 3. Standard cell/ model/… Design & Layout library maintenance. 4. CAD tool evaluation, usage, maintenance & contact with EDA vendor. 5. EDA license maintain. 6. Provide training, documentation & user support. 7. 熟悉Synopsys, Cadence, mentor EDA 軟體.
1天以前更新 兩週內0-5人應徵
2021-10-19

Analog CAD Engineer

FULL_TIME
新竹縣竹北市
M31 Technology Corporation_円星科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1. PDK Installation and QA and maintenance 2. Schematic related tools maintenance and automation programming. 3. IC Layout related tools maintenance and automation programming. 4. Can use TCL to process Layout database and related automation programs on Laker / CCSE / Virtuoso
6天以前更新 兩週內0-5人應徵
2021-10-14
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Foundry & In-house DRC/LVS/LPE/PERC rule deck maintain & creation 2. Physical verification CAD flow establishment & maintenance 3. Issue solving for ASIC project & IP development DRC/LVS problem
三週以前更新 兩週內0-5人應徵
2021-09-29

Physical IP CAD Engineer

FULL_TIME
新竹縣竹北市
英屬維京群島商爍星有限公司台灣分公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1. EDA kits (Verilog, LEF, liberty) establishment, quality analysis and delivery for digital IPs 2. Liberty (NLDM,CCS,LVF…) characterization, quality analysis and flow establishment for digital IPs 3. Spice-netlist/GDS generation, Quality analysis and delivery for digital IPs 4. Design flow automation and in-house tool development
2天以前更新 兩週內0-5人應徵
2021-10-18

Analog CAD Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. IP design flow development 2. In-house utility development for IP design 3. EDA tool evaluation, usage, maintenance, Q&A window with tool vendor 4. 具備programming 能力 ( C/C++, TCL script, C-shell 或perl 其中一項以上 ) 5. Familiar with Virtuoso SKILL writing, Calibre rule writing, or other EDA tools is a plus. ※Requirements: 1. 熟 Verilog language, Verilog simulator 2. 有IP beh
一週以前更新 兩週內0-5人應徵
2021-10-12
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
三週以前更新 兩週內0-5人應徵
2021-09-29
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Front-end design flow development 2. Logic Synthesis, STA, LEC, ECO flow creation and consultant
三週以前更新 兩週內0-5人應徵
2021-09-29

數字IP工程师/ Digital CAD Engineer

FULL_TIME
新竹縣竹北市
台灣矽力杰科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
提供數字/混模電路設計的CAD 支持,負責公司内部數字IP 模塊的開發和外部IP Vendor 的技術聯絡。 Digital CAD Engineer, working as part of the CAD team on development and support of digital and mixed signal design flows, driving the in-house development of digital IP building block, and acting as the primary technical liaison between the company and external IP vendors
一個月以前更新 兩週內0-5人應徵
2021-09-08

Memory CAD Engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Implement memory compiler design utilities. 2. Develop memory IP design flow. 3. Familiar with C/C++, Tcl, and c shell. 4. Familiar with memory design, it’s plus 5. Familiar with liberty, verilog, tessent or DFT models, it’s plus
三週以前更新 兩週內0-5人應徵
2021-09-29

Cell Library CAD engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
As an Cell Library CAD engineer, you will be in charge of one of following job functions: 1. Standard cell library characterization flow development 2. Standard cell library front-end model generation and verification flow development 3. IP backend model generation and QA flow development and maintaining 4. IP behavior model creation and maintaining
三週以前更新 兩週內0-5人應徵
2021-09-29

數位IC設計工程師 (CAD engineer)

FULL_TIME
新竹縣竹北市
DIGWISE_崛智科技有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1) Build up IP behavior model. 2) Memory compiler development. 3) Standard cell library re-k; cell analyze, debug, and PPA. 4) Support company design flow related script; script writing, utility programming.
6天以前更新 兩週內0-5人應徵
2021-10-14

Standard Cell CAD Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://bit.ly/3pacoi0 Description 1.Play a strategic role of applying AI/machine-learning techniques to your (and colleagues’) daily work, including circuit design analysis, characterization, QA, and silicon debug. 2.Be the expert of library design kit and lead TSMC-EDA-IC design cooperation. 3.Provide end-
一個月以前更新 兩週內0-5人應徵
2021-09-13
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