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1708 筆查詢結果

DFT CAD Flow Engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Study / research / develop DFT design flow 2. Maintain inhouse DFT utilities.
三週以前更新 兩週內0-5人應徵
2021-09-29

DFT CAD Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT design methodology development. (2) Flow development for MBIST, SCAN & ATPG. (3) In-house DFT design-kit/utility/script development.
一週以前更新 兩週內0-5人應徵
2021-10-12

CAD Engineer/Manager

FULL_TIME
新竹市
晶豪科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Tools automation script. 2. LVS and DRC rule maintenance. 3. Standard cell/ model/… Design & Layout library maintenance. 4. CAD tool evaluation, usage, maintenance & contact with EDA vendor. 5. EDA license maintain. 6. Provide training, documentation & user support. 7. 熟悉Synopsys, Cadence, mentor EDA 軟體.
2天以前更新 兩週內0-5人應徵
2021-10-19

DFT Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1.Development and implementation for advanced at speed testing and DFT, JTAG, MBIST, SCAN Chain and ATPG. 2.Requirement: 2-1. BS or MS degree in EE or related. 2-2. Familiar with DFT related flow and EDA tools 2-3. Experience in Logic simulation flow (e.g. Cadence NCVerilog or Synopsys VCS). 2-4. Experience in chip design flow and chip implementation flow is a plus. 2-5. Proficient in Tcl a
6天以前更新 兩週內11-30人應徵
2021-10-15

CAD Department Manager

FULL_TIME
新竹市
華晶科技股份有限公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
1. Lead the team to build up the front end EDA environment ( synthesis, STA, equivalence checking, static/dynamic verification and low power UPF verification) 2. EDA tools and environment management 3. Support RD PM to collaborate with backend service company
1天以前更新 兩週內0-5人應徵
2021-10-20

DFT Engineer

FULL_TIME
新竹市
益芯科技股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
(1)BS degree in EE of related experience. (2)Familiar with IC design flow and DFT.
6天以前更新 兩週內0-5人應徵
2021-10-15

Frontend CAD工程師

FULL_TIME
新竹縣竹北市
松翰科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
‧BS or MS degree in EE or related. ‧At least 2~3 years experience on Frontend CAD / implementation. ‧Familiar with Synthesis/Formal/STA/DFT flow ‧Familar with EDA tool including Cadence RTL Compiler/LEC/ ETS && Mentor Fastscan is plus . ‧Familiar with cell library characterization,C shell/Perl script is plus
13小時以前更新 兩週內0-5人應徵
2021-10-21
台灣超捷國際股份有限公司
  • 大學以上
  • 八年以上工作經驗
  • 待遇面議
Job Description: In this position, you will be responsible for all the DFT related matters in Microchip's Wireless SoC Development. Your scope of work includes but not limited to: • Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan. • Work closely with front-end
1天以前更新 兩週內0-5人應徵
2021-10-20
虹晶科技股份有限公司
  • 碩士
  • 十年以上工作經驗
  • 待遇面議
工作內容 ‧Communicate with customers to provide suitable test architecture planning for project scopce.. ‧Working with the APR team to ensure to correct DFT implementation and closing timing ‧Simulating and verifying the ATPG patterns ‧Analyzing and working with the different stakeholders to get the required design changes in to get the maximum ATPG coverage ‧Developing, enhancing and mainta
5天以前更新 兩週內0-5人應徵
2021-10-16
台灣超捷國際股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
Job Description: In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless SoC Development. Your scope of work includes but not limited to: • Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan. • Work closely with front-end te
1天以前更新 兩週內0-5人應徵
2021-10-20
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. Study / research / develop DFT design flow 2. Maintain inhouse DFT utilities. 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. 熟悉 DFT概念及EDA Tool者為佳 3. 熟悉 C/C++ or Tcl ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
7小時以前更新 兩週內0-5人應徵
2021-10-21
台灣超捷國際股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
Job Description: In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless SoC Development. Your scope of work includes but not limited to: • Perform DFT logic insertion and stitching into RTL code or netlists using EDA/CAD tools for ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST, and Boundary Scan. • Work closely with front-end t
1天以前更新 兩週內0-5人應徵
2021-10-20

SSD Design Flow Engineer

FULL_TIME
新竹縣竹北市
慧榮科技股份有限公司_SMI
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Digital IC designer 2. RTL coding/simulation 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools.
兩週以前更新 兩週內6-10人應徵
2021-10-04

DFT Implementation Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT planning & implementation for MBIST/SCAN/ATPG/BSCAN... (2) Perform STA & timing closure for DFT modes. (3) Create DFT test pattern & perform DFT Verilog simulation. (4) Co-work with Test Engineers to bring-up testing in ATE.
一週以前更新 兩週內0-5人應徵
2021-10-12
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
三週以前更新 兩週內0-5人應徵
2021-09-29
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