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DV Methodology Engineer

FULL_TIME
新竹市
聯發科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
由於 先進製程 與 高整合度晶片 需要 較長的研發時間 及 高製造成本, DV (Design Verification) 已成為 聯發科技 晶片開發流程中 不可或缺的一環 . CDG DV部門負責 開發與執行 最高整合度 Smartphone, TV 與 ASIC 驗證工程. 內容包含: 整合型驗證環境開發, 大數據分析與效能改善, BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行. 工作中需要 設計 及 精進 Verification plan/methodology/be
4天以前更新 兩週內0-5人應徵
2021-10-12

DV Engineer/數位設計驗證工程師

FULL_TIME
新竹縣竹北市
SK hynix_台灣愛思開海力士科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
Looking for ASIC Verification Engineer, responsible for 1. Working with ASIC design and architecture teams to understand the functionality of logic blocks 2. Develop and drive verification plans 3. Generate constrained random and directed tests to implement verification plan 4. Run simulations and debug issues 5. Create verification test bench components to monitor and check design 6. Create
1天以前更新 兩週內0-5人應徵
2021-10-15

ASIC Flow Automation Engineer

FULL_TIME
新竹縣竹北市
松翰科技股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1. ASIC flow automation process 2. Use EDA tool to verify design quality (EX: SPYGLASS, DFT, STA, LEC, Synthesis)
三週以前更新 兩週內0-5人應徵
2021-09-22

ASIC Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for digital designer with solid digital design and technical skills. The responsibility is to deliver Sub-System level design and corresponding verification environment for high performance System-on-Chip. 2.Responsible for RTL, integration and verification of IP and customer specific digital design content. Expect to contribute to methodology development and effic
4天以前更新 兩週內0-5人應徵
2021-10-12
科締納科技股份有限公司_Cortina Systems Taiwan Limited
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
Senior level ASIC design engineer [Responsibility] Module level design and verification activities including: • Design digital control or datapath logic using Verilog HDL • Design synthesis using RTL Complier • RTL linting using preferred lint tool SoC integration FPGA design and lab debug
兩週以前更新 兩週內0-5人應徵
2021-09-27

SoC/ASIC/IP digital design engineer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
- Design/development of SoC subsystem blocks. - Responsible for SOC system Integration/Verification - Generate detailed micro-architecture technical specifications and systems requirements and deliver the design - Work closely with verification team to develop verification plans and actively participate in debug phase - Work hands-on and own their design through the full SoC/ASIC development p
4天以前更新 兩週內0-5人應徵
2021-10-12

ASIC/ECC DESIGN Engineer (Hsinchu)

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
• You will be involved in developing storage chipsets. • The work requires participation in defining functional specifications with the ASIC architect and developing the design in Verilog. • Support verification, circuit, and test groups throughout the design cycle and silicon bring up. • Work with multi-disciplinary groups to ensure designs are delivered on time and with the highest quality
一週以前更新 兩週內0-5人應徵
2021-10-05
智原科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASI
兩週以前更新 兩週內0-5人應徵
2021-09-29
毅誠電子有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
工作項目: 數位IC/IP 設計開發與維護,FPGA驗證 應徵條件: 1. 碩士以上; 電機工程、電子工程等相關科系畢業為主。 2. 熟悉digital circuit design。 3, 具Verilog 相關經驗、熟悉FPGA/ASIC發展流程。 4, 具 peripheral bus (SPI, SMBUS, UART) 經驗者佳 5, 熟悉 AMBA protocol. 6. 熟悉 高速介面(SATA, PCIE) 規格 或相關經驗者佳 7. 具有數位IC設計 工作經歷 2年以上
一週以前更新 兩週內0-5人應徵
2021-10-09

ASIC Engineer (新竹)

FULL_TIME
新竹市
印正有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1. Writing testbench and /or run mix-mode simulation. 2. Writing sensor timing control HDL code. 3. ISP(Image Signal Processing) development, HDL code and model. 4. Familiar with system-verilog is a plus. 5. Familiar with EDA tool is a plus(DC/PTIME/FORMAL/TESSENT/…) 6. Familiar with Customsim(XA) or Finesim is a plus. 7. Familiar with Xilinx FPGA development(design & debugging) is plus.
2天以前更新 兩週內0-5人應徵
2021-10-14
Qualcomm Semiconductor Corporation_高通半導體有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Job Overview: Position corresponds to development of ARM architecture based complex CPU subsystem. Engineer will work in a dynamic and consumer oriented environment where both time to market and quality are extremely important. CPU sub-system design development includes: • CPU sub-system feature enhancement, micro-architecture, and RTL development • Integration of CPU and other relevant IPs into t
2天以前更新 兩週內0-5人應徵
2021-10-14
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
Micron is seeking an ASIC Development - Chip Lead for Micron’s ASIC project. In this role, you will be responsible for leading development of SOC design in our storage-based controllers from Specification to transfer to volume production. You should have strong knowledge and proven hands-on experience with many aspects of the SOC design and implementation flow – including coverage driven verificat
三週以前更新 兩週內0-5人應徵
2021-09-17

ASIC Frontend 設計工程師

FULL_TIME
新竹縣竹北市
聯發科技集團_達發科技股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1.Responsible ASIC frontend flow, including synthesis, DFT, STA, LEC, PTPX, CTS, UPF, Timing constraints closure,PnR co-work. 2.RTL design optimization for timing closure.
2天以前更新 兩週內0-5人應徵
2021-10-14

ASIC Product Engineer

FULL_TIME
新竹市
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 五年以上工作經驗
  • 待遇面議
Micron’s vision is to transform how the world uses information to enrich life for all. ​ Join an inclusive team focused on one thing: using our expertise in the relentless pursuit of innovation for customers and partners. The solutions we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainabi
三週以前更新 兩週內0-5人應徵
2021-09-17
擷發科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
The verification tasks include block level, chip level verification, test plan creation, scripting, coverage, regression run etc...
3天以前更新 兩週內0-5人應徵
2021-10-13
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