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964 筆查詢結果

Digital ASIC Design Engineer

FULL_TIME
新竹市
瑞典商_芬格科技有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
To strengthen and building up our new ASIC team in Hsinchu, Taiwan, we are looking for Digital ASIC Design Engineers who wants to make a difference and strengthen the development of Fingerprint’s sensor technology. You will report directly to the ASIC Manager/Project Manager in Hsinchu. We offer you an exciting and challenging position together with friendly and professional colleagues. Work in a
4天以前更新 兩週內0-5人應徵
2021-12-01

Analog ASIC Design Engineer

FULL_TIME
新竹市
瑞典商_芬格科技有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
To strengthen and building up our new ASIC team in Hsinchu, Taiwan, we are looking for Analog ASIC design engineers who wants to make a difference and strengthen the development of Fingerprint’s sensor technology. You will report directly to the ASIC Manager/Project manager in Hsinchu. We offer you an exciting and challenging position together with friendly and professional colleagues. Work in an
4天以前更新 兩週內0-5人應徵
2021-12-01

ASIC Project Manager

FULL_TIME
新竹市
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.全球ASIC project leader 2.與客戶討論ASIC project spec, project management 3.管理ASIC計畫並管理ASIC project進度, project從cooking到量產
2天以前更新 兩週內6-10人應徵
2021-12-03

ASIC DV Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for DV engineer with solid digital verification technical skills. The responsibility is to deliver high-performance SOC with the highest standard of quality for world-wide customer in the process of 16nm or under. 2.This position will be responsible for working with Design Engineers in verification and validation of SOC. Participate in design reviews and recommend
6天以前更新 兩週內0-5人應徵
2021-11-29

ASIC Design Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1.We are looking for digital designer with solid digital design and technical skills. The responsibility is to deliver Sub-System level design and corresponding verification environment for high performance System-on-Chip. 2.Responsible for RTL, integration and verification of IP and customer specific digital design content. Expect to contribute to methodology development and effic
6天以前更新 兩週內0-5人應徵
2021-11-29
科締納科技股份有限公司_Cortina Systems Taiwan Limited
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
Senior level ASIC design engineer [Responsibility] Module level design and verification activities including: • Design digital control or datapath logic using Verilog HDL • Design synthesis using RTL Complier • RTL linting using preferred lint tool SoC integration FPGA design and lab debug
5天以前更新 兩週內0-5人應徵
2021-11-30

Design Verification Manager

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
1. Development of the verification infrastructure in UVM/System Verilog for block-level/chip-level design verification. 2. Create and maintain detailed test plans to ensure the quality and performance are met. Define and implement functional coverage, and enhance the test bench to ensure coverage closure. 3. Participate in design reviews and recommend improvements. Collaborate with ASIC and Firmwa
一週以前更新 兩週內0-5人應徵
2021-11-26
台灣特納飛科技有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Responsible for the creation and management of a design verification group with ownership over various parts of a complex state-of-the-art SOC, from team building, to test planning, to test bench and test development, simulation and debugging, regression, documentation, coverage measurement, all the way to tape out and post-silicon validation. Must be hands-on and able to act as a technical lea
4天以前更新 兩週內0-5人應徵
2021-12-01
科締納科技股份有限公司_Cortina Systems Taiwan Limited
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting
兩個月以前更新 兩週內0-5人應徵
2021-09-22
擷發科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Develop and maintain block and chip level verification environment 2. Execute and manage test plan 3. In charge of Subsystem DV for SPEC-IN Project 1.block 與 chip level 驗證環境開發與維護 2.規劃與執行測試項目 3.依據規格負責子系統驗證
兩週以前更新 兩週內0-5人應徵
2021-11-20

ASIC/ECC DESIGN Engineer (Hsinchu)

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 專科以上
  • 工作經驗不拘
  • 待遇面議
• You will be involved in developing storage chipsets. • The work requires participation in defining functional specifications with the ASIC architect and developing the design in Verilog. • Support verification, circuit, and test groups throughout the design cycle and silicon bring up. • Work with multi-disciplinary groups to ensure designs are delivered on time and with the highest quality
一週以前更新 兩週內0-5人應徵
2021-11-26

SoC/ASIC/IP digital design engineer

FULL_TIME
新竹縣竹北市
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
- Design/development of SoC subsystem blocks. - Responsible for SOC system Integration/Verification - Generate detailed micro-architecture technical specifications and systems requirements and deliver the design - Work closely with verification team to develop verification plans and actively participate in debug phase - Work hands-on and own their design through the full SoC/ASIC development p
6天以前更新 兩週內0-5人應徵
2021-11-29

Design Verification Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1. Digital Design Verification 2. Work with digital design team to define verification plan . 3. Develop in house VIP 4. Use standard protocol VIP 5. Verify RTL design ※Requirements: 1. Familiarity with OOP , has design patter knowledge is plus 2. Familiarity with Systemverilog , has UVM experience is plus 3. Experience in IP verification 4. VIP use Experience
5天以前更新 兩週內0-5人應徵
2021-11-30

ASIC Physical Design

FULL_TIME
新竹縣竹北市
Western Digital_新加坡商西部數據有限公司台灣分公司
  • 大學 碩士
  • 四年以上工作經驗
  • 待遇面議
Job Description 1. Has Physical Design experience (Perform complete netlist to GDS physical design steps which include floor plan, CTS, APR, timing closure, IR/EM analysis, layout verification, formal verification, timing ECO, and other tape out related tasks. Candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requir
6天以前更新 兩週內0-5人應徵
2021-11-29
台灣美光(台灣美光晶圓科技股份有限公司/台灣美光記憶體股份有限公司/美商美光亞太科技股份有限公司台灣分公司)
  • 大學 碩士
  • 十年以上工作經驗
  • 待遇面議
As a Design Verification Engineer within the ASIC CXL Development at Micron, you will be responsible for defining efficient and coverage-driven testbench for high-quality design delivery. Job Responsibilities: Verification plan definition, DV environment development in SV/UVM and SV/C Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level. Suppor
兩個月以前更新 兩週內0-5人應徵
2021-07-14
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