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Marvell_邁威爾科技有限公司
  • 大學以上
  • 十年以上工作經驗
  • 待遇面議
The Opportunity In this highly visible role, you will be responsible for the technical management, planning, organization, work breakdown, and allocation of all analog chip level and macros level of custom layout efforts, leading a team of expert layout designers. Additional responsibilities include utilizing your hands-on layout experience, contributing to analog layout of related macros, as well
1天以前更新 兩週內0-5人應徵
2022-01-27
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Design and optimize transistor level circuits (analog/mixed-signal) for high-speed SerDes IP. 2. Behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems. 3. Supervise layout. 4. Silicon bring up, characterization, and debugging. 5. Design and silicon documentation. 6. Work with cross functional teams to bring IP from schematics to mass productio
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱。 ※Job Contents: 1. SOC ESD review / check. 2. ESD/PERC rules & ESD methodology development. 3. PERC results checking ※Requirements(Engineer): 1. Familiar with circuit theory, device physics and ESD protection concept 2. Familiar with PERC, Calibre, Layout Editor, Perl, Unix shell 3. Over 3 year experiences. ※Requirements(Technical Manager): 1. Familiar with circuit design is
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士以上
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1.Task leading for the front-end design from RTL to netlist. 2.Main job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA. 3.Support other functional teams (such as IP team, DFT team, and P&R team) to deliver an SoC/ASIC. 4.Use communication and leadership skills to help the team to achieve the goal. ※Requirements: 1.碩士
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. Package/PCB Model extraction by EM tooling. 2. Whole system level signal/power integrity modeling, characterization and simulations including PCB, package and chip IOs. 3. Silicon chip results correlation with simulation 4. Co-simulation flow development 5. Co-work with IC designer to define specification and solve the silicon related signal and power integrity problems in the s
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 專科 大學
  • 一年以上工作經驗
  • 待遇面議
※Job Contents: 1.Mix mode 2.Analog layout 3.Full Customer Layout ※Requirements: 1.具類比IP、special I/O、Mixed mode full custom layout經驗。 2.具full custom IC layout / verification經驗。 3.具 Laker/Virtuoso, Calibre LVS / DRC/ Calibre等工具經驗。 4.具16/ 7/5nm IC layout experiences is a plus. 5.歡迎有IC layout經驗3年以上者加入。 **此職缺適用於自我推薦獎金獎勵** 自我推薦獎金辦法: 1.期間限定:202
4天以前更新 兩週內6-10人應徵
2022-01-24
創意電子股份有限公司
  • 碩士
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Reliability plan deployment, read-out execution and schedule control 2. Reliability circuit board design and layout check 3. Reliability contact window for qualification plan negotiation with customers 4. Electrostatic damage and Latch-Up test research 5. Internal cross-team communication and coordination ※Requirements: 1. 電子/電機/物理/材料或其它工科相關科系之碩士 2. 有興趣或
4天以前更新 兩週內11-30人應徵
2022-01-24
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 ※Job Contents: 1. 2.5D IC Physical Design (Interposer) 2. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 3. Support STA timing analysis and fixing 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Synopsys ICC2/Fusion Compiler or Cadence
4天以前更新 兩週內6-10人應徵
2022-01-24
創意電子股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
DFT Design Engineer - MBIST / SCAN ※Job Contents: 1. 工作地點:台北/新竹/台南. 2. Implement of MBIST / SCAN 3. Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check 4. Discuss with Test Engineers to provide solutions to DFT testing ※Requirements: 1. Graduated in EE or related Engineering 2. Proficient in programming skill and UNIX shell. 3. Familiar with Verilog / RTL
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
Job description: a. Cell library and foundry process technology file management b. Technical support for standard cell and technology file related issues c. Circuit simulation and characterization d. Cell optimization for power and performance Nice to have: 1. Experience in cell library or circuit design 2. Advanced process (N16 and beyond) cell timing / power modeling experience is plus 3. Has
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
[Responsibilities] 1.Work closely with all IP (R&D) engineering teams to provide support for all activities in the product development and customer support. 2.With coordination with IP (R&D) teams, communicate and work with customer. 3.To support customer engagement and work with sales for IP promotion. 4.To management IP product documents. [Skills & Qualifications] 1.Degree in Engineering
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Engage customer and IP promotion. 2. IP issue tracking and technical support. ※Requirements(either one of below items) 1. IP design/integration Experience. 2. Familiar with either one of the below protocols:PCIe/Ethernet/SATA/HBM/DDR and knowledge of system debugging. 3. Rich experiences to deal engagement and customer support. **此職缺適用於自我推薦獎金獎勵** 自我推薦獎金辦法
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. 3rd-party SRAM/TCAM/NVM IP and standard cell technical support 2. Memory re-characterization 3. Customer spec clarification & solution provision 4. IP deliverable Qualification 5. IP validation consulting 6. Post-silicon IP  bring up & analyzing ※Requirements: 1. Education: Master Degree in EE or related 2. Technical Background: 3+ years memory IP design experience. 3. Language:
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis, routing and Tape-out sign off. 2. Familiar IP & Testchip APR flow develoment. 3. Support STA timing analysis and fixing. 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. 6. Familiar with APR tools (Cadence Innovus or Synopsys ICC2.) 7
4天以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士
  • 十年以上工作經驗
  • 待遇面議
※Job Contents: 1. Work with GUC's customers to define a competitive packaging solution. 2. Package design, solve technical challenge, and all package related actions follow up. 3. Work with GUC signal integrity engineer, substrate designer and thermal designer to come up with a cost effective package. 4. New package technology design flow development ※Requirements: 1.機械/電子/電機工程/材料工程相
4天以前更新 兩週內0-5人應徵
2022-01-24
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