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Standard cell CAD engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,主要負責Standard cell應用端效能最佳化分析。 1.Pre-layout/Post-layout PPA analysis 2.Standard cell design and layout optimization 3.Technical support of in-house & 3rd-party libraries。 4.需求條件: 4-1. 熟悉 physical design flow 4-2. 具備physical design PPA and routability 分析經驗尤佳 4-3. 具備high speed synthesis, DFT, or STA sign-off經驗尤佳 4-4.
5天以前更新 兩週內0-5人應徵
2022-01-18

CAD Engineer

FULL_TIME
新竹市
智成電子股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1. Front-end IC design flow development/maintain/support 2. Standard cell library design & modeling & maintain 3. IC tape out project support
一個月以前更新 兩週內0-5人應徵
2021-12-01

Cell Library CAD engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
As an Cell Library CAD engineer, you will be in charge of one of following job functions: 1. Standard cell library characterization flow development 2. Standard cell library front-end model generation and verification flow development 3. IP backend model generation and QA flow development and maintaining 4. IP behavior model creation and maintaining
一個月以前更新 兩週內0-5人應徵
2021-11-29

CAD Engineer

FULL_TIME
新竹縣竹北市
萬有半導體有限公司
  • 大學
  • 三年以上工作經驗
  • 待遇面議
CAD Projects - Adding and improving grid/Isf tools (Linux) - Automation of project setup and user adding (Linux) - CAD tool license usage monitors (Linux) - Noisy Sensitive Tools (Front End, Back End) - Simulation batch run tools (Front End) CAD Ongoing Tasks: - Creating and archiving projects (Linux) - Adding Users to projects (Linux) - Setting up Jira users and projects (Application) - Setting
4天以前更新 兩週內0-5人應徵
2022-01-19

CAD Engineer

FULL_TIME
新竹市
瓦雷科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.
2天以前更新 兩週內0-5人應徵
2022-01-21

Staff CAD Engineer

FULL_TIME
新竹市
台灣英飛朗股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 年薪 1,500,000 ~ 3,000,000 元
Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of t
2天以前更新 兩週內0-5人應徵
2022-01-21

Standard Cell Library Engineer

FULL_TIME
新竹縣竹北市
松翰科技股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1. Analog-IP liberty characterization and creation 2. Re-K Standard cell liberty 3. Verilog behavior model 4. Siliconsmart characterization flow/script establishment and maintenance 5. Run HSPICE & Verilog Simulation to confirm the correctness of the .lib/.v model
3天以前更新 兩週內0-5人應徵
2022-01-20

數字IP工程师/ Digital CAD Engineer

FULL_TIME
新竹縣竹北市
台灣矽力杰科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
提供數字/混模電路設計的CAD 支持,負責公司内部數字IP 模塊的開發和外部IP Vendor 的技術聯絡。 Digital CAD Engineer, working as part of the CAD team on development and support of digital and mixed signal design flows, driving the in-house development of digital IP building block, and acting as the primary technical liaison between the company and external IP vendors
一週以前更新 兩週內0-5人應徵
2022-01-13
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Foundry & In-house DRC/LVS/LPE/PERC rule deck maintain & creation 2. Physical verification CAD flow establishment & maintenance 3. Issue solving for ASIC project & IP development DRC/LVS problem
一個月以前更新 兩週內0-5人應徵
2021-12-03
Intel_美商英特爾亞太科技有限公司台灣分公司
  • 大學以上
  • 四年以上工作經驗
  • 待遇面議
Foundry Technology Engineering (FTE) group under Global External Manufacturing and Sourcing (GEMS) is looking for a highly motivated and experienced individual to be part of an exciting engineering team dedicated to enabling and supporting Foundation IPs for Intel design projects (such as client, server, core, atom, graphics, mixed-signal IPs and other SoC projects) to be successful on external fo
3天以前更新 兩週內6-10人應徵
2022-01-20
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
一個月以前更新 兩週內0-5人應徵
2021-12-03

Standard cell design engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
任職於Design Engineering Service (DES) 部門,負責Standard cell設計及效能最佳化分析、In-house cell library開發、3rd party cell library維護。 1.Standard cell circuit design and optimization。 2.Library design methodology development。 3.Cell characterization and library generation。 4.Library QA and maintenance。 5.Technical support of in-house & 3rd-party libraries。 【共創A+聯詠】 穩健踏實、專
5天以前更新 兩週內0-5人應徵
2022-01-18
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Front-end design flow development 2. Logic Synthesis, STA, LEC, ECO flow creation and consultant
一個月以前更新 兩週內0-5人應徵
2021-12-03
104獵才顧問_一零四資訊科技股份有限公司
  • 學歷不拘
  • 三年以上工作經驗
  • 待遇面議
1. 負責standard cell architecture 開發
兩週以前更新 兩週內0-5人應徵
2022-01-05

CAD工程師(CAD Engineer)(2022-014)

FULL_TIME
新竹縣竹北市
力智電子股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
Develop methodology for design automation CAD system administrator APR
一週以前更新 兩週內0-5人應徵
2022-01-11
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