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SoC Physical Design Engineer(新竹)

FULL_TIME
新竹縣竹北市
英屬開曼群島商世芯股份有限公司台灣分公司
  • 大學 碩士
  • 一年以上工作經驗
  • 待遇面議
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achi
3天以前更新 兩週內0-5人應徵
2021-07-21
Qualcomm Semiconductor Corporation_高通半導體有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
QCTs CPU Subsystem Team in Taiwan is actively seeking engineers for the CPU Subsystem Physical Design Team. As a physical design engineer you will innovate, develop, and implement CPU cores using state-of-the-art tools and technologies. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design implementations for high performance SoCs in sub-
1天以前更新 兩週內0-5人應徵
2021-07-23

APR Physical Design工程師

FULL_TIME
新竹縣竹北市
香港商鑫澤數碼股份有限公司台灣分公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1.Perform Netlist-to-GDS design flow of SOC chip/SYS/Block. 2.TOP level floorplan, block partition, block integration, timing closure and tapeout. 3.Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4.High speed IP implementation, DDR, GPU, CPU.
5天以前更新 兩週內0-5人應徵
2021-07-19
聯詠科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 3.Requirement: 3-1. Familiar with ASIC design flow相關尤佳 3-2. Hands on APR physical design from netlist to DRC/LVS tapeout experience is required 3-3. Familiar with hierarchical and/or low power design flow相關尤佳
一個月以前更新 兩週內11-30人應徵
2021-06-17

Physical Design Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR Implementation. - floorplan, placement, clock tree synthesis - routing, timing optimization. 2. Physical verification. (DRC/LVS) 3. Timing Closure. - STA - PT, Tweaker 4. Power analysis and fixing (IR/EM). 5. Low power implementation. - UPF flow
一週以前更新 兩週內0-5人應徵
2021-07-14

CPU Physical designer

FULL_TIME
新竹市
聯發科技股份有限公司
  • 碩士
  • 八年以上工作經驗
  • 待遇面議
CPU Physical design - floorplanning - timing closure - Physical verficiation - DFT
1天以前更新 兩週內0-5人應徵
2021-07-23
天鈺科技股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
Develop physical design methodology and implementation.
4天以前更新 兩週內0-5人應徵
2021-07-20
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1.SoC Chip Top and Infrastructure integration and physical design 2.Participate in SoC design implementation from logic synthesis to physical implementation stage under the latest technology process
1天以前更新 兩週內0-5人應徵
2021-07-23
聯詠科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Physical design of multi-million instance-count SOC project. Physical design activities include floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. (APR Support) 2.Build advanced physical design methodology to facilitate UDSM design project for timing/power/DFM closure and CPU/GPU hardening. 3.Requirement: 3-1. Familiar with Cadence EDI Platform and/or Syno
一個月以前更新 兩週內0-5人應徵
2021-06-17

Physical Design Engineer APR

FULL_TIME
新竹市
104獵才顧問
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.
2天以前更新 兩週內0-5人應徵
2021-07-22

Physical Design Engineer

FULL_TIME
新竹市
益芯科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Must have BS in EE/CE/CS of relevant experience in IC design field. 2. Familiar with IC design flow : *Chip integration and floorplan *APR physical design *Fully customized layout *DRC/LVS to tapeout 3. Engineering discipline, passion, and willing to teamwork. 4. Circuit knowledge and analog/logic design relevant experience would be a plus.
5天以前更新 兩週內0-5人應徵
2021-07-19

Physical Design Engineer

FULL_TIME
新竹市
翊傑科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
經歷不拘 1. Location:新竹 2. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 3. Support STA timing analysis and fixing 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. 5. Perform power analysis / IR drop analysis ※Requirements: 1. Familiar with Cadence EDI or other auto place and route t
3天以前更新 兩週內0-5人應徵
2021-07-21

Physical Design APR Engineer

FULL_TIME
新竹縣竹北市
M31 Technology Corporation_円星科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop analysis. 4. Familiar with Synopsys ICC/ ICC2 or Cadence Innovus 5. tcl or perl script language skill is preferred.
3天以前更新 兩週內0-5人應徵
2021-07-21
創意電子股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis, routing and Tape-out sign off. 2. Familiar IP & Testchip APR flow develoment. 3. Support STA timing analysis and fixing. 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. 6. Familiar with APR tools (Cadence Innovus or Synopsys ICC2.) 7
5天以前更新 兩週內0-5人應徵
2021-07-19
智原科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.
2天以前更新 兩週內6-10人應徵
2021-07-22
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