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Digital IC Design Engineer

FULL_TIME
新竹縣竹北市
台灣瑞阩科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
Digital IC design, verification and physical implementation. Synthesis, STA, timing closure. FPGA integration. [ Digital IC Desing Engineer - I ] Experience in audio/voice signal processing (Filter, EQ, DRC.. ) is preferred. Digital IP design and verification. [ Digital IC Desing Engineer - II ] SoC integration(floorplan design, package bonding) and verification Power domain design.
4天以前更新 兩週內0-5人應徵
2021-10-19

Digital IC Design Engineer

FULL_TIME
新竹市
衡宇科技股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
1. RTL module design 2. Pre-sim and Post-sim 3. Quality check: Lint, code coverage, CDC 4. Synthesis, static timing and formal check 5. FPGA compilation and debug
2天以前更新 兩週內0-5人應徵
2021-10-21

Digital IC Design Engineer

FULL_TIME
新竹縣竹北市
英屬維京群島商視芯智能股份有限公司台灣分公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
•設計與實現computer vision 相關數位IP •熟悉C/C++, Verilog, 和EDA 前端工具 •支援AE 驗證FPGA以及IC量產 •有團隊精神,對於新創的生態和新的題目有適應能力和自信
1天以前更新 兩週內0-5人應徵
2021-10-22

Digital IC Design Engineer (Hsinchu)

FULL_TIME
新竹縣竹北市
睿寬智能科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Digital IC design, or verification, or FPGA, or STA timing closure. Algorithm, DSP, Communication. SOC development flow, from architect, Specification, design, verification, timing closure, tape out, mass-production. Verilog and/or writing shell/tcl scripts. 2. Good sense of debug, meaning, identify the root cause, resolve the problem. Working with Design, Verification, FW teams. Po
兩週以前更新 兩週內0-5人應徵
2021-10-05
NXP Semiconductors Taiwan Ltd._台灣恩智浦半導體股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
***Please upload English resume onto our official platform: https://lnkd.in/gk3hK5m MSEE or equivalent preferred Strong DSP fundamentals Strong digital communication fundamentals Strong VLSI fundamentals Capable in scripting/programming for test automation and data manipulation/analysis (Python, Perl) Strong problem solving and analytical skills Well organized and have the ability to be flexible
兩週以前更新 兩週內6-10人應徵
2021-10-09

Sr./Staff Digital IC Design Engineer

FULL_TIME
新竹縣竹北市
萬典科技股份有限公司
  • 大學 碩士
  • 四年以上工作經驗
  • 待遇面議
1. HDL coding and design verification for TDDI products 2. System validation/debug and customer issues support 3. CP test pattern generation and co-work with test engineer for CP testing 4. Area/power optimization, and design trade-off analysis 5. Lint/ CDC analysis for digital design 6. Schedule tasks and goals to complete designs on time that meet all specifications
3天以前更新 兩週內0-5人應徵
2021-10-20
芯偉有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Design the digital part of the high-speed standard physical layer, such as PCIe, USB, HDMI, DP, etc. 2. Co-work with the analog designer to implement the analog adaptors, such as calibration mechanism, DSP algorithm, etc. 3. Digital front-end flow, such as Spyglass, Design Compiler, Formality, Primetime, etc. (The scripts are supported by the CAD team). 4. Co-work with the APR engineer for the
三週以前更新 兩週內0-5人應徵
2021-09-27
睿寬智能科技有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
1. Expertise in digital IC design, or verification, or FPGA, or STA timing closure. (at least One of them). 2. Experience in SOC development flow, from architect, design, verification, timing closure, tape out, mass-production. 3. Experience of Verilog and/or writing shell/tcl scripts. 4. Good sense of debug, meaning, identify the root cause, resolve the problem. 5. Working with Design,
兩週以前更新 兩週內0-5人應徵
2021-10-05
Spring Professional_藝珂人事顧問股份有限公司躍科分公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
1. 協助多家台灣知名IC設計公司獵才 2. 需要有3年以上的相關經驗 , 經理職需要有10年以上相關經驗及帶領團隊經驗 3. 有 WiFi MAC / Driver IC / Power 擇一相關經驗 4. 公司地點 : 台北 / 新竹皆有
2天以前更新 兩週內0-5人應徵
2021-10-21
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Et
一週以前更新 兩週內0-5人應徵
2021-10-12
多方科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
[Responsibilities] Work with a team to: - Plan design architecture. - Develop high quality digital design. - Be familiar with IC design flow. [Qualifications] Minimum Qualifications: - MS degree in Electrical Engineering, Computer Science or related field. - Proficient in Verilog coding and verification. - Experienced in front-end IC design flow. Preferred Qualifications: - Expe
1天以前更新 兩週內0-5人應徵
2021-10-22
多方科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
[Responsibilities] - ARM series CPU integration -System bus architecture design and implementation [Professional Experience] - Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) - Experienced in ARM cache, MMU, TCM design - Experienced in system bus architecture (AMBA AHB/AXI) design - Experienced in SoC chip integration [Qualifications] Minimum Qualifications: - Out
1天以前更新 兩週內0-5人應徵
2021-10-22
創意電子股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1. PCIe PCS and PHY digital design 自我推薦獎金辦法: 1.期間限定:2021/10/01-2021/12/31 2.適用職缺: 職缺上有註明”享自我推薦獎金,獎金最高15萬”者適用 3.獎勵內容: 相關年資1年(含)-未滿3年:NT$ 3萬元/位 相關年資3年(含)-未滿5年:NT$ 5萬元/位 相關年資5年(含)-未滿8年:NT$ 8萬元/位 相關年資8年(含)以上:NT$ 12萬元/位 應徵者若為前GUC員工,另加碼NT$ 3萬元/位 4.核發方式:報到後滿6個月時發給全額獎金。 5.應徵
一週以前更新 兩週內0-5人應徵
2021-10-12
M31 Technology Corporation_円星科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1. Design and integrate for High Speed SerDes IP 2. Verify SerDes IP controller and sub-system 3. Co-work with functional team on debugging and integration 4. Design and IP documentation
2天以前更新 兩週內0-5人應徵
2021-10-21
創未來科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 月薪 78,000 ~ 140,000 元
## Job Description: The candidate will work closely with DSP algorithm team and software team to propose functional architecture and implement DSP algorithm using RTL and verified on a Xilinx FPGA. The verified design will either be passed to back-end for P&R or as a FPGA device product for early customer demo. The candidate will work with massive I/O throughputs using a parallel of high speed se
3天以前更新 兩週內0-5人應徵
2021-10-20
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