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聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
- Develop robust 3DIC PDN considering PDN impacts - Build and analyze 3DIC IR results and propose solutions - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches - Explore EDA tool new features and introduce to project team
3天以前更新 兩週內0-5人應徵
2022-01-20
Qualcomm Semiconductor Corporation_高通半導體有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
Qualcomm Power Integrity group is looking for a power integrity engineer to work on power integrity analysis and optimization of next generation of application processors, graphic processors and modems for mobile, auto and wireless LAN platforms. Job responsibilities include SOC floor planning, system optimization, package /PCB optimization and characterization as well silicon package PCB co-des
2天以前更新 兩週內0-5人應徵
2022-01-21
聯發科技股份有限公司
  • 碩士以上
  • 六年以上工作經驗
  • 待遇面議
* DFM rule creation based on layout environment for process weakness * DTCO for PPA enhancement * Testline creation for process and device monitor
5天以前更新 兩週內0-5人應徵
2022-01-18
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1 Develop the Timing signoff criterion for leading process node and 3DIC. 2 Maintain the Timing signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing violation 3 Develop new Timing signoff methodology to be applied during chip synthesis/APR/STA. 4 SPICE correlation for new timing signoff criterion 5 Regression test for every signoff methodology by S
5天以前更新 兩週內0-5人應徵
2022-01-18

Power Analysis Engineer

FULL_TIME
新竹市
聯發科技股份有限公司
  • 碩士以上
  • 八年以上工作經驗
  • 待遇面議
1. Establish and drive low power state and corresponding product power goals. 2. Identify power optimization techniques applicable at different design levels. 3. EDA tool management and support 4. Power Profiling
5天以前更新 兩週內0-5人應徵
2022-01-18
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
• Provide SI/PI support to local & overseas field application engineers to ensure customer board performance • Review customer board layout & schematics for SI design rule compliance and power rail decoupling • Collaborate with PCB layout engineers to design & optimize test boards • Perform board-level EM simulations to optimize interconnects for impedance, skew, and crosstalk • Conduct IR drop &
3天以前更新 兩週內0-5人應徵
2022-01-20
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1 Develop the Timing/IR signoff criterion for leading process node and 3DIC. 2 Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/IR violation 3 Develop new Timing/IR signoff methodology to be applied during chip synthesis/APR/STA/IR .
5天以前更新 兩週內0-5人應徵
2022-01-18
創意電子股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
※依學經歷核定職稱 Physical Design Technical Manager (APR) ※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Com
6天以前更新 兩週內0-5人應徵
2022-01-17
啟碁科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. Switch Power Integrity and Signal Integrity量測及分析 2. CPU Board Power Integrity量測 及分析 3. 高速訊號儀器環境維護及調校 4. SI/PI實驗室建置
兩個月以前更新 兩週內0-5人應徵
2021-10-19
智邦科技股份有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
Senior Power/Signal Integrity engineering positions available at Accton Technology in Silicon Valley and Taiwan. Top expertise in AC and DC Power Integrity analysis, simulations, and measurements are a must. Excellence in setting up and running simulations in Sigrity PowerDC, OptimizePI, or Advanced PI, Advanced SI, is a plus. Excellent communicator specifically interfacing with hyperscale data ce
一個月以前更新 兩週內0-5人應徵
2021-12-02
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※依學經歷核定職稱 1.Develop power and IR verification methodology to ensure chip power integrity. 2.Perform IR verification, including power calculation, IR drop and EM analysis, and library power modeling. 3.Develop design flow to analyze the quality of power delivery network, including power grid, bump assignment, and chip-package co-design. 4.Support power network improvement. Job Requirements
6天以前更新 兩週內0-5人應徵
2022-01-17
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1 Develop the IR signoff criterion for leading process node and 3DIC. 2 Maintain the IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable IR violation 3 Develop new IR signoff methodology to be applied during chip synthesis/APR/STA/IR . 4 SPICE correlation for new IR signoff criterion 5 Regression test for every signoff methodology by IR results
3天以前更新 兩週內0-5人應徵
2022-01-20
乾瞻科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1.Whole system signal and power integrity modeling and simulation including IP (DDR and other interface IP such as MIPI, PCIE, etc.), package and PCB. 2.Package and PCB model extraction for SI/PI simulation. 3.Co-work with IP designers to simulate and solve IP and system level SI/PI issues.
5天以前更新 兩週內0-5人應徵
2022-01-18
創意電子股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
Job description: a. Cell library and foundry process technology file management b. Technical support for standard cell and technology file related issues c. Circuit simulation and characterization d. Cell optimization for power and performance Nice to have: 1. Experience in cell library or circuit design 2. Advanced process (N16 and beyond) cell timing / power modeling experience is plus 3. Has
6天以前更新 兩週內0-5人應徵
2022-01-17
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://bit.ly/3py6JRB Description 1. Optimization, Meta-Heuristic algorithm, A.I. solution research & development. 2. Initial, innovate, develop and introduce Intelligent Manufacturing Solutions. 3. System analysis, design, development and integration for cross organizations/systems projects. Qualifications
兩個月以前更新 兩週內0-5人應徵
2021-09-13
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