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Dialog Semiconductor_德商戴樂格半導體有限公司台灣分公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
The Role Working as a Principal/Senior Mixed Signal Verification Engineer based in Zhubei, you will: • Develop analog circuit models and system models that enable efficient and accurate verification of functionality and connectivity within the integrated system, and update the models as needed as their design progresses. • Work with designers to ensure that the developed models are adequate func
6天以前更新 兩週內0-5人應徵
2021-10-13

Senior Digital Verification Engineer

FULL_TIME
新竹縣竹北市
Dialog Semiconductor_德商戴樂格半導體有限公司台灣分公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
The Role Working as a Senior Digital Verification Engineer based in Zhubei, you will: • Define testbench infrastructure using SystemVerilog, UVM and Formal. • Responsible for complete digital level verification. • Modeling of analog functions in SystemVerilog. • Responsible for complete chip level verification of mixed signal IC. • Work closely with design team to architect a new design verificat
6天以前更新 兩週內0-5人應徵
2021-10-13

CPU IP Verification Engineer

FULL_TIME
新竹市
安興技術諮詢股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
Job description Are you a passionate verification engineer who loves to work on complex systems, building test environments which find all the bugs before anyone else find them? Do you pay attention to the latest in verification technologies to make sure you're as efficient as possible while working on increasingly complicated IPs? We have fantastic opportunities for experienced and highly motiva
兩個月以前更新 兩週內0-5人應徵
2021-03-11

Design Verification Engineer

FULL_TIME
新竹縣竹北市
耐能智慧股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to delive
一個月以前更新 兩週內0-5人應徵
2021-09-09

Mix-Signal Verification Engineer

FULL_TIME
新竹縣竹北市
聯發科技集團_立錡科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1.Develop real-numbered models in System Verilog 2.Develop analog and mixed-signal behavioral models in Verilog-A / AMS 3.Implement simulation testbenches to verify the usage scenarios of designs. 4.Work closely with analog and/or digital design team to ensure the models are adequate for simulation
一個月以前更新 兩週內0-5人應徵
2021-08-24
創意電子股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
※Job Descriptions: 1.SoC/Subsystem verification : Job includes IP simulation bring up and testbench promote to subsystem/chip level 2.SoC/Subsystem design : Job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, STA and FPGA verification. ※Job Requirements: 1.MS or PhD degree in EE, CS, or relevant fields 2.Good at verification skills such as UVM
一週以前更新 兩週內0-5人應徵
2021-10-12
Dialog Semiconductor_德商戴樂格半導體有限公司台灣分公司
  • 大學以上
  • 七年以上工作經驗
  • 待遇面議
• Develop analog circuit models and system models that enable efficient and accurate verification of functionality and connectivity within the integrated system, and update the models as needed as their design progresses. • Work with designers to ensure that the developed models are adequate functional models of their sub-system blocks. • Implement simulation testbenches/tests that verify the prod
6天以前更新 兩週內0-5人應徵
2021-10-13
美商超微半導體股份有限公司台灣分公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand col
6天以前更新 兩週內0-5人應徵
2021-10-13

Design Verification Engineer

FULL_TIME
新竹市
系統精英科技股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
1.SoC design verification 2. System verification
一週以前更新 兩週內0-5人應徵
2021-10-12
瑞昱半導體股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification
6天以前更新 兩週內0-5人應徵
2021-10-13
安霸股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
At Ambarella, we gather brilliant minds together to push computer vision technology forward. We're seeking a VLSI design verification (DV) engineer who will verify our most cutting-edge SOCs and components inside SOC. A DV engineer works with designers to make sure design meets specification. Firstly, a DV engineer creates a test plan. A test plan plots in details on what tests you need/want
4天以前更新 兩週內0-5人應徵
2021-10-15
NVIDIA_英屬維京群島商輝達維京股份有限公司台灣分公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
We're looking for a Senior Digital Design Verification Engineer. As a Senior Mixed Signal Digital Design Verification engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a world-class team that deliver
3天以前更新 兩週內0-5人應徵
2021-10-16

Design Verification Engineer (UVM)

FULL_TIME
新竹縣竹北市
香港商默升科技有限公司台灣分公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
- Knowledge of System Verilog, digital simulation and debug. - Exposure to UVM is desired. - Familiar with USB design is a plus.
4天以前更新 兩週內0-5人應徵
2021-10-15

SoC Verification Engineer

FULL_TIME
新竹市
瑞昱半導體股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.Writing behavioral model 2.Responsible for functional verification
6天以前更新 兩週內11-30人應徵
2021-10-13

SoC Verification Engineer

FULL_TIME
新竹縣竹北市
藍芯微電子有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Writing behavioral model 2.Responsible for functional verification 3.Set up simulation environment and flow to support FPGA evaluation
4天以前更新 兩週內0-5人應徵
2021-10-15
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